Subversion Repositories bustap-jtag

 PARAMETER VERSION = 2.1.0


 PORT PS_SRSTB = PS_SRSTB, DIR = I
 PORT PS_CLK = PS_CLK, DIR = I, SIGIS = CLK
 PORT PS_PORB = PS_PORB, DIR = I
 PORT PS_DDR_Clk = PS_DDR_Clk, DIR = IO, SIGIS = CLK
 PORT PS_DDR_Clk_n = PS_DDR_Clk_n, DIR = IO, SIGIS = CLK
 PORT PS_DDR_CKE = PS_DDR_CKE, DIR = IO
 PORT PS_DDR_CS_n = PS_DDR_CS_n, DIR = IO
 PORT PS_DDR_RAS_n = PS_DDR_RAS_n, DIR = IO
 PORT PS_DDR_CAS_n = PS_DDR_CAS_n, DIR = IO
 PORT PS_DDR_WEB = PS_DDR_WEB, DIR = O
 PORT PS_DDR_BankAddr = PS_DDR_BankAddr, DIR = IO, VEC = [2:0]
 PORT PS_DDR_Addr = PS_DDR_Addr, DIR = IO, VEC = [14:0]
 PORT PS_DDR_ODT = PS_DDR_ODT, DIR = IO
 PORT PS_DDR_DRSTB = PS_DDR_DRSTB, DIR = IO, SIGIS = RST
 PORT PS_DDR_DQ = PS_DDR_DQ, DIR = IO, VEC = [31:0]
 PORT PS_DDR_DM = PS_DDR_DM, DIR = IO, VEC = [3:0]
 PORT PS_DDR_DQS = PS_DDR_DQS, DIR = IO, VEC = [3:0]
 PORT PS_DDR_DQS_n = PS_DDR_DQS_n, DIR = IO, VEC = [3:0]
 PORT PS_DDR_VRN = PS_DDR_VRN, DIR = IO
 PORT PS_DDR_VRP = PS_DDR_VRP, DIR = IO
 PORT PS_MIO = PS_MIO, DIR = IO, VEC = [53:0]


BEGIN processing_system7
 PARAMETER INSTANCE = PS
 PARAMETER HW_VER = 4.02.a
 PARAMETER C_DDR_RAM_HIGHADDR = 0x3FFFFFFF
 PARAMETER C_EN_EMIO_CAN0 = 0
 PARAMETER C_EN_EMIO_CAN1 = 0
 PARAMETER C_EN_EMIO_ENET0 = 0
 PARAMETER C_EN_EMIO_ENET1 = 0
 PARAMETER C_EN_EMIO_I2C0 = 0
 PARAMETER C_EN_EMIO_I2C1 = 0
 PARAMETER C_EN_EMIO_PJTAG = 0
 PARAMETER C_EN_EMIO_SDIO0 = 0
 PARAMETER C_EN_EMIO_CD_SDIO0 = 0
 PARAMETER C_EN_EMIO_WP_SDIO0 = 0
 PARAMETER C_EN_EMIO_SDIO1 = 0
 PARAMETER C_EN_EMIO_CD_SDIO1 = 0
 PARAMETER C_EN_EMIO_WP_SDIO1 = 0
 PARAMETER C_EN_EMIO_SPI0 = 0
 PARAMETER C_EN_EMIO_SPI1 = 0
 PARAMETER C_EN_EMIO_SRAM_INT = 0
 PARAMETER C_EN_EMIO_TRACE = 0
 PARAMETER C_EN_EMIO_TTC0 = 1
 PARAMETER C_EN_EMIO_TTC1 = 0
 PARAMETER C_EN_EMIO_UART0 = 0
 PARAMETER C_EN_EMIO_UART1 = 0
 PARAMETER C_EN_EMIO_MODEM_UART0 = 0
 PARAMETER C_EN_EMIO_MODEM_UART1 = 0
 PARAMETER C_EN_EMIO_WDT = 1
 PARAMETER C_EN_QSPI = 1
 PARAMETER C_EN_SMC = 0
 PARAMETER C_EN_CAN0 = 1
 PARAMETER C_EN_CAN1 = 0
 PARAMETER C_EN_ENET0 = 1
 PARAMETER C_EN_ENET1 = 0
 PARAMETER C_EN_I2C0 = 1
 PARAMETER C_EN_I2C1 = 0
 PARAMETER C_EN_PJTAG = 0
 PARAMETER C_EN_SDIO0 = 1
 PARAMETER C_EN_SDIO1 = 0
 PARAMETER C_EN_SPI0 = 0
 PARAMETER C_EN_SPI1 = 0
 PARAMETER C_EN_TRACE = 0
 PARAMETER C_EN_TTC0 = 1
 PARAMETER C_EN_TTC1 = 0
 PARAMETER C_EN_UART0 = 0
 PARAMETER C_EN_UART1 = 1
 PARAMETER C_EN_MODEM_UART0 = 0
 PARAMETER C_EN_MODEM_UART1 = 0
 PARAMETER C_EN_USB0 = 1
 PARAMETER C_EN_USB1 = 0
 PARAMETER C_EN_WDT = 1
 PARAMETER C_EN_DDR = 1
 PARAMETER C_EN_GPIO = 1
 PARAMETER C_FCLK_CLK0_FREQ = 100000000
 PARAMETER C_FCLK_CLK1_FREQ = 50000000
 PARAMETER C_FCLK_CLK2_FREQ = 50000000
 PARAMETER C_FCLK_CLK3_FREQ = 50000000
 PARAMETER C_USE_M_AXI_GP0 = 1
 PARAMETER C_USE_M_AXI_GP1 = 1
 PARAMETER C_USE_CR_FABRIC = 1
 PARAMETER C_NUM_F2P_INTR_INPUTS = 7
 PARAMETER C_USE_S_AXI_GP0 = 0
 PARAMETER C_USE_S_AXI_GP1 = 0
 PARAMETER C_USE_S_AXI_HP0 = 1
 PARAMETER C_USE_S_AXI_HP1 = 1
 PARAMETER C_USE_S_AXI_HP2 = 1
 PARAMETER C_USE_S_AXI_HP3 = 1
 PARAMETER C_S_AXI_HP0_BASEADDR = 0x00000000
 PARAMETER C_S_AXI_HP0_HIGHADDR = 0x3FFFFFFF
 PARAMETER C_EMIO_GPIO_WIDTH = 64
 PARAMETER C_EN_EMIO_GPIO = 0
 BUS_INTERFACE M_AXI_GP0 = AXI_PS_PL
 PORT PS_SRSTB = PS_SRSTB
 PORT PS_CLK = PS_CLK
 PORT PS_PORB = PS_PORB
 PORT FCLK_CLK0 = PS_FCLK_CLK0
 PORT DDR_Clk = PS_DDR_Clk
 PORT DDR_Clk_n = PS_DDR_Clk_n
 PORT DDR_CKE = PS_DDR_CKE
 PORT DDR_CS_n = PS_DDR_CS_n
 PORT DDR_RAS_n = PS_DDR_RAS_n
 PORT DDR_CAS_n = PS_DDR_CAS_n
 PORT DDR_WEB = PS_DDR_WEB
 PORT DDR_BankAddr = PS_DDR_BankAddr
 PORT DDR_Addr = PS_DDR_Addr
 PORT DDR_ODT = PS_DDR_ODT
 PORT DDR_DRSTB = PS_DDR_DRSTB
 PORT DDR_DQ = PS_DDR_DQ
 PORT DDR_DM = PS_DDR_DM
 PORT DDR_DQS = PS_DDR_DQS
 PORT DDR_DQS_n = PS_DDR_DQS_n
 PORT DDR_VRN = PS_DDR_VRN
 PORT DDR_VRP = PS_DDR_VRP
 PORT MIO = PS_MIO
 PORT M_AXI_GP1_ACLK = clock_generator_0_CLKOUT0
 PORT M_AXI_GP0_ARESETN = PS_M_AXI_GP0_ARESETN
 PORT M_AXI_GP0_ACLK = clock_generator_0_CLKOUT0
 PORT S_AXI_HP0_ACLK = clock_generator_0_CLKOUT0
 PORT S_AXI_HP1_ACLK = clock_generator_0_CLKOUT0
 PORT S_AXI_HP2_ACLK = clock_generator_0_CLKOUT0
 PORT S_AXI_HP3_ACLK = clock_generator_0_CLKOUT0
 PORT FCLK_RESET0_N = PS_FCLK_RESET0_N
END

BEGIN bram_block
 PARAMETER INSTANCE = PL_bram_block
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = axi_bram_ctrl_1_BRAM_PORTA
 BUS_INTERFACE PORTB = axi_bram_ctrl_1_BRAM_PORTB
END

BEGIN axi_bram_ctrl
 PARAMETER INSTANCE = PL_bram_ctrl
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_S_AXI_BASEADDR = 0x40000000
 PARAMETER C_S_AXI_HIGHADDR = 0x40000FFF
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = PS.M_AXI_GP0
 BUS_INTERFACE S_AXI = AXI_PS_PL
 BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_1_BRAM_PORTA
 BUS_INTERFACE BRAM_PORTB = axi_bram_ctrl_1_BRAM_PORTB
 PORT S_AXI_ACLK = clock_generator_0_CLKOUT0
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = AXI_PS_PL
 PARAMETER HW_VER = 1.06.a
 PORT INTERCONNECT_ACLK = clock_generator_0_CLKOUT0
 PORT INTERCONNECT_ARESETN = PS_M_AXI_GP0_ARESETN
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 4.03.a
 PARAMETER C_CLKIN_FREQ = 100000000
 PARAMETER C_CLKOUT0_FREQ = 75000000
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_CLKOUT1_FREQ = 50000000
 PARAMETER C_CLKOUT2_FREQ = 0
 PORT CLKIN = PS_FCLK_CLK0
 PORT RST = PS_FCLK_RESET0_N
 PORT CLKOUT0 = clock_generator_0_CLKOUT0
END

BEGIN bustap_jtag
 PARAMETER INSTANCE = bustap_jtag_0
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE MON_AXI = PS.M_AXI_GP0
 PORT ACLK = clock_generator_0_CLKOUT0
 PORT CHIPSCOPE_ICON_CONTROL0 = chipscope_icon_0_control0
 PORT CHIPSCOPE_ICON_CONTROL1 = chipscope_icon_0_control1
 PORT CHIPSCOPE_ICON_CONTROL2 = chipscope_icon_0_control2
END

BEGIN chipscope_icon
 PARAMETER INSTANCE = chipscope_icon_0
 PARAMETER HW_VER = 1.06.a
 PARAMETER C_NUM_CONTROL_PORTS = 3
 PORT control0 = chipscope_icon_0_control0
 PORT control1 = chipscope_icon_0_control1
 PORT control2 = chipscope_icon_0_control2
END