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[/] [bustap-jtag/] [trunk/] [rtl/] [xilinx/] [coregen/] [chipscope_vio_fifo.v] - Rev 20
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/////////////////////////////////////////////////////////////////////////////// // Copyright (c) 2014 Xilinx, Inc. // All Rights Reserved /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 14.3 // \ \ Application: Xilinx CORE Generator // / / Filename : chipscope_vio_fifo.v // /___/ /\ Timestamp : Fri Feb 07 17:33:59 中国标准时间 2014 // \ \ / \ // \___\/\___\ // // Design Name: Verilog Synthesis Wrapper /////////////////////////////////////////////////////////////////////////////// // This wrapper is used to integrate with Project Navigator and PlanAhead `timescale 1ns/1ps module chipscope_vio_fifo( CONTROL, CLK, SYNC_IN, SYNC_OUT) /* synthesis syn_black_box syn_noprune=1 */; inout [35 : 0] CONTROL; input CLK; input [107 : 0] SYNC_IN; output [1 : 0] SYNC_OUT; endmodule