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https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk
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[/] [bustap-jtag/] [trunk/] [rtl/] [xilinx/] [coregen/] [chipscope_vio_mask.v] - Rev 25
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/////////////////////////////////////////////////////////////////////////////// // Copyright (c) 2012 Xilinx, Inc. // All Rights Reserved /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 14.2 // \ \ Application: Xilinx CORE Generator // / / Filename : chipscope_vio_mask.v // /___/ /\ Timestamp : Tue Nov 20 10:36:39 中国标准时间 2012 // \ \ / \ // \___\/\___\ // // Design Name: Verilog Synthesis Wrapper /////////////////////////////////////////////////////////////////////////////// // This wrapper is used to integrate with Project Navigator and PlanAhead `timescale 1ns/1ps module chipscope_vio_mask( CONTROL, CLK, SYNC_OUT); inout [35 : 0] CONTROL; input CLK; output [39 : 0] SYNC_OUT; endmodule
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