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## clock pin for Nexys 2 Board 
#NET "clk_i" LOC= "B8"; # Bank = 0 , Pin name = IP_L13P_0/GCLK8 , Type = GCLK , Sch name = GCLK0
 
NET "vgaRed<5>"   LOC = "R9";
NET "vgaRed<6>"   LOC = "T8"; 
NET "vgaRed<7>"   LOC = "R8"; 
NET "vgaGreen<5>" LOC = "N8"; 
NET "vgaGreen<6>" LOC = "P8";
NET "vgaGreen<7>" LOC = "P6";
NET "vgaBlue<6>"  LOC = "U5"; 
NET "vgaBlue<7>"  LOC = "U4"; 
NET "vga_rsync_o" LOC = "T4"; 
NET "vga_fsync_o" LOC = "U3";
#
NET "pix_data_i<0>"  LOC = "B4";
NET "pix_data_i<1>"  LOC = "A4";
NET "pix_data_i<2>"  LOC = "C3";
NET "pix_data_i<3>"  LOC = "C4";
NET "pix_data_i<4>"  LOC = "B6";
NET "pix_data_i<5>"  LOC = "D5";
NET "pix_data_i<6>"  LOC = "C5";
NET "pix_data_i<7>"  LOC = "F7";
NET "fsync_i" LOC = "A8";
NET "rsync_i" LOC = "D7";
NET "rsync_i" CLOCK_DEDICATED_ROUTE = FALSE;
NET "pclk_i" LOC = "A11";
NET "pclk_i" CLOCK_DEDICATED_ROUTE = FALSE;

# Leds
NET "led0_o" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
NET "led1_o" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
NET "led2_o" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
NET "led3_o" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
#NET "led4_o" LOC = "E16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD4? other than s3e500
#NET "led5_o" LOC = "P16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD5? other than s3e500
#NET "led6_o" LOC = "E4";  # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD6? other than s3e500
#NET "led7_o" LOC = "P4";  # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD7? other than s3e500

# RS232 connector
NET "RX_i" LOC = "U6"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = RS-RX
NET "TX_o" LOC = "P9"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = RS-TX

# 12 pin connectors
#NET "JA<0>" LOC = "L15"; # Bank = 1, Pin name = IO_L09N_1/A11, Type = DUAL, Sch name = JA1
#NET "JA<1>" LOC = "K12"; # Bank = 1, Pin name = IO_L11N_1/A9/RHCLK1, Type = RHCLK/DUAL, Sch name = JA2
#NET "JA<2>" LOC = "L17"; # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Sch name = JA3
#NET "JA<3>" LOC = "M15"; # Bank = 1, Pin name = IO_L07P_1, Type = I/O, Sch name = JA4
#NET "JA<4>" LOC = "K13"; # Bank = 1, Pin name = IO_L11P_1/A10/RHCLK0, Type = RHCLK/DUAL, Sch name = JA7
#NET "JA<5>" LOC = "L16"; # Bank = 1, Pin name = IO_L09P_1/A12, Type = DUAL, Sch name = JA8
#NET "JA<6>" LOC = "M14"; # Bank = 1, Pin name = IO_L05P_1, Type = I/O, Sch name = JA9
#NET "JA<7>" LOC = "M16"; # Bank = 1, Pin name = IO_L07N_1, Type = I/O, Sch name = JA10
#NET "JB<0>" LOC = "M13"; # Bank = 1, Pin name = IO_L05N_1/VREF_1, Type = VREF, Sch name = JB1
#NET "JB<1>" LOC = "R18"; # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL, Sch name = JB2
#NET "JB<2>" LOC = "R15"; # Bank = 1, Pin name = IO_L03P_1, Type = I/O, Sch name = JB3
#NET "JB<3>" LOC = "T17"; # Bank = 1, Pin name = IO_L01N_1/A15, Type = DUAL, Sch name = JB4
#NET "JB<4>" LOC = "P17"; # Bank = 1, Pin name = IO_L06P_1, Type = I/O, Sch name = JB7
#NET "JB<5>" LOC = "R16"; # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF, Sch name = JB8
#NET "JB<6>" LOC = "T18"; # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL, Sch name = JB9
#NET "JB<7>" LOC = "U18"; # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL, Sch name = JB10
#NET "JC<0>" LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O, Sch name = JC1
#NET "JC<1>" LOC = "J16"; # Bank = 1, Pin name = IO_L13N_1/A5/RHCLK5, Type = RHCLK/DUAL, Sch name = JC2
#NET "JC<2>" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
#NET "JC<3>" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
#NET "JC<4>" LOC = "H15"; # Bank = 1, Pin name = IO_L17N_1, Type = I/O, Sch name = JC7
#NET "JC<5>" LOC = "F14"; # Bank = 1, Pin name = IO_L21N_1, Type = I/O, Sch name = JC8
#NET "JC<6>" LOC = "G16"; # Bank = 1, Pin name = IO_L18N_1, Type = I/O, Sch name = JC9
#NET "JC<7>" LOC = "J12"; # Bank = 1, Pin name = IO_L15P_1/A2, Type = DUAL, Sch name = JC10
#NET "JD<0>" LOC = "J13"; # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL, Sch name = JD1
#NET "JD<1>" LOC = "M18"; # Bank = 1, Pin name = IO_L08N_1, Type = I/O, Sch name = JD2
#NET "JD<2>" LOC = "N18"; # Bank = 1, Pin name = IO_L08P_1, Type = I/O, Sch name = JD3
#NET "JD<3>" LOC = "P18"; # Bank = 1, Pin name = IO_L06N_1, Type = I/O, Sch name = JD4

# 7 segment display
#NET "seg8_cathode_o<0>" LOC = "L18"  | IOSTANDARD=LVTTL; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Sch name = CA
#NET "seg8_cathode_o<1>" LOC = "F18"  | IOSTANDARD=LVTTL; # Bank = 1, Pin name = IO_L19P_1, Type = I/O, Sch name = CB
#NET "seg8_cathode_o<2>" LOC = "D17"  | IOSTANDARD=LVTTL; # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL, Sch name = CC
#NET "seg8_cathode_o<3>" LOC = "D16"  | IOSTANDARD=LVTTL; # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL, Sch name = CD
#NET "seg8_cathode_o<4>" LOC = "G14"  | IOSTANDARD=LVTTL; # Bank = 1, Pin name = IO_L20P_1, Type = I/O, Sch name = CE
#NET "seg8_cathode_o<5>" LOC = "J17"  | IOSTANDARD=LVTTL; # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = CF
#NET "seg8_cathode_o<6>" LOC = "H14"  | IOSTANDARD=LVTTL; # Bank = 1, Pin name = IO_L17P_1, Type = I/O, Sch name = CG
#NET "seg8_cathode_o<7>" LOC = "C17"  | IOSTANDARD=LVTTL; # Bank = 1, Pin name = IO_L24N_1/LDC2, Type = DUAL, Sch name = DP
#
#NET "seg8_anode_o<0>" LOC = "F17"  | IOSTANDARD=LVTTL; # Bank = 1, Pin name = IO_L19N_1, Type = I/O, Sch name = AN0
#NET "seg8_anode_o<1>" LOC = "H17"  | IOSTANDARD=LVTTL; # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL, Sch name = AN1
#NET "seg8_anode_o<2>" LOC = "C18"  | IOSTANDARD=LVTTL; # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL, Sch name = AN2
#NET "seg8_anode_o<3>" LOC = "F15"  | IOSTANDARD=LVTTL; # Bank = 1, Pin name = IO_L21P_1, Type = I/O, Sch name = AN3

# Switches
NET "sw_i<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0
NET "sw_i<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1
NET "sw_i<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2
NET "sw_i<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3
NET "sw_i<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4
NET "sw_i<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5
NET "sw_i<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6
#NET "sw_i<7>" LOC = "R17"  | IOSTANDARD=LVTTL; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7

NET "reset_i" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7

#===============================================================================
# USB interface
#===============================================================================
#NET "fpgalink_fx2Clk_i"        LOC="T15"  | IOSTANDARD=LVTTL;   # IFCLK
#NET "fpgalink_fx2Clk_i" CLOCK_DEDICATED_ROUTE = FALSE;
#NET "fpgalink_fx2Addr_o<0>"    LOC="T14"  | IOSTANDARD=LVTTL;   # PA4/FIFOADR0
#NET "fpgalink_fx2Addr_o<1>"    LOC="V13"  | IOSTANDARD=LVTTL;   # PA5/FIFOADR1
#
#NET "fpgalink_fx2Data_io<0>"   LOC="R14"  | IOSTANDARD=LVTTL;   # PB0/FD0
#NET "fpgalink_fx2Data_io<1>"   LOC="R13"  | IOSTANDARD=LVTTL;   # PB1/FD1
#NET "fpgalink_fx2Data_io<2>"   LOC="P13"  | IOSTANDARD=LVTTL;   # PB2/FD2
#NET "fpgalink_fx2Data_io<3>"   LOC="T12"  | IOSTANDARD=LVTTL;   # PB3/FD3
#NET "fpgalink_fx2Data_io<4>"   LOC="N11"  | IOSTANDARD=LVTTL;   # PB4/FD4
#NET "fpgalink_fx2Data_io<5>"   LOC="R11"  | IOSTANDARD=LVTTL;   # PB5/FD5
#NET "fpgalink_fx2Data_io<6>"   LOC="P10"  | IOSTANDARD=LVTTL;   # PB6/FD6
#NET "fpgalink_fx2Data_io<7>"   LOC="R10"  | IOSTANDARD=LVTTL;   # PB7/FD7
#
#NET "fpgalink_fx2Read_o"       LOC="N9"   | IOSTANDARD=LVTTL;   # RDY0/SLRD
#NET "fpgalink_fx2OE_o"         LOC="V15"  | IOSTANDARD=LVTTL;   # PA2/SLOE
#NET "fpgalink_fx2GotData_i"    LOC="V16"  | IOSTANDARD=LVTTL;   # CTL2/FLAGC
#
#NET "fpgalink_fx2Write_o"      LOC="V9"   | IOSTANDARD=LVTTL;   # RDY1/SLWR
#NET "fpgalink_fx2GotRoom_i"    LOC="U14"  | IOSTANDARD=LVTTL;   # CTL1/FLAGB
#NET "fpgalink_fx2PktEnd_o"     LOC="V12"  | IOSTANDARD=LVTTL;   # PA6/PKTEND