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[/] [cheap_ethernet/] [trunk/] [Ethernet_test/] [ipcore_dir/] [FIFORX.xise] - Rev 3
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
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<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="FIFORX.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="FIFORX.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
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<property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|FIFORX" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="FIFORX.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/FIFORX" xil_pn:valueState="non-default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
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<property xil_pn:name="PROP_DesignName" xil_pn:value="FIFORX" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-08-28T17:12:10" xil_pn:valueState="non-default"/>
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</project>