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[/] [cic_core_2/] [trunk/] [rtl/] [verilog/] [integrator.sv] - Rev 4
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`timescale 1ns / 1ns
module integrator
/*********************************************************************************************/
#(parameter DATA_WIDTH_INP = 8 , DATA_WIDTH_OUT = 9)
/*********************************************************************************************/
(
input clk,
input reset_n,
input clear,
input wire signed [DATA_WIDTH_INP - 1:0] inp_samp_data,
input inp_samp_str,
output reg signed [DATA_WIDTH_OUT - 1:0] out_samp_data
);
/*********************************************************************************************/
wire signed [DATA_WIDTH_OUT - 1:0] sum;
assign #4 sum = out_samp_data + inp_samp_data; // delay for 18x18 multiplier of Cyclone V SE is 3.4 ns
always @(posedge clk or negedge reset_n)
begin
if (!reset_n) out_samp_data <= '0;
else if (clear) out_samp_data <= '0;
else if (inp_samp_str) out_samp_data <= sum;
end
/*********************************************************************************************/
endmodule
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