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[/] [claw/] [trunk/] [or1200_cpu/] [work/] [or1200_cfgr/] [_primary.vhd] - Rev 4
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library verilog; use verilog.vl_types.all; entity or1200_cfgr is port( spr_addr : in vl_logic_vector(31 downto 0); spr_dat_o : out vl_logic_vector(31 downto 0) ); end or1200_cfgr;