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Wishbone Verification IP</a></span>
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February 5th, 2010 | Author: <a href="about" title="Author">Tiksan</a>
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<p>The Wishbone Verification IP is a simple solution for verification of Wishbone B3 master and slave devices. The provided Wishbone verification package includes master and slave SystemVerilog verification IPs and examples. It will help engineers to quickly create verification environment end test their Wishbone master and slave devices. <span id="more-495"></span></p>
<p>You can download the Wishbone Verification IP from <a href="http://syswip.com/downloads">Downloads</a> page.</p>
<p><strong><span style="font-size: 16px;">Features</span></strong></p>
<ol>
<li>Free SystemVerilog source code</li>
<li>Easy integration and usage</li>
<li>Compliant to Wishbone B3 Protocol</li>
<li>Operates as a Master or Slave</li>
<li>Supports 1, 2, 4 and 8 bytes data block size</li>
<li>Supports single cycle transfers</li>
<li>Supports wait states injection</li>
<li>Supports programmable retry and error insertion</li>
<li>Supports full random timings</li>
<li>Supports misaligned transfers</li>
</ol>
<p><strong><span style="font-size: 16px;">Limitations</span></strong></p>
<ol>
<li>Doesn’t support TAGs</li>
<li>Doesn’t support Lock signal</li>
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<p><strong><span style="font-size: 16px;">Installation</span></strong></p>
<ol>
<li>Download <a href="http://syswip.com/download/wishbone_vip.zip">Wishbone Verification IP</a> and unpack it.</li>
<li>If you want to run examples
<ol>
<li>Go to the following folder: <unpack_dir>/wishbone_vip/examples/sim</li>
<li>For VCS type the following command: vcs -f file_list.f -sverilog</li>
<li>For QuestaSim6.4 type the following command: qverilog -f file_list.f</li>
</ol>
</li>
<li>Please read the Wishbone Verification IP User Manual.</li>
</ol>
<p><strong><span style="font-size: 16px;">Support</span></strong></p>
<p>If you have any questions please don’t hesitate <a href="http://syswip.com/contacts">to contact me</a>.</p>
<p>You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!</p>
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Posted in <a href="http://syswip.com/category/systemverilog-verification-ip" title="View all posts in SystemVerilog Verification IP" rel="category tag">SystemVerilog Verification IP</a>, <a href="http://syswip.com/category/systemverilog-verification-ip/wishbone-bus-verification-ip" title="View all posts in Wishbone bus Verification IP" rel="category tag">Wishbone bus Verification IP</a>
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<h3 id="comments">4 Responses to “Wishbone Verification IP”</h3>
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<cite class="fn">kaku817</cite> <span class="says">says:</span> </div>
<div class="comment-meta commentmetadata"><a href="http://syswip.com/wishbone-verification-ip/comment-page-1#comment-568">January 7, 2011 at 3:47 am</a></div>
<p>Hi,</p>
<p>Thanks for your works for “Wishbone Verification IP”.<br />
It is very helpful for me.</p>
<p>How about to support Wishbone B4 version that<br />
contains pipeline transfer hand-shaking?</p>
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<cite class="fn">Tiksan</cite> <span class="says">says:</span> </div>
<div class="comment-meta commentmetadata"><a href="http://syswip.com/wishbone-verification-ip/comment-page-1#comment-569">January 7, 2011 at 9:31 am</a></div>
<p>Hi kaku817,</p>
<p>Thank you very much for informing me about Wishbone B4.<br />
I will find the time to implement this new version.<br />
Bests Tiksan.</p>
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<cite class="fn">mathieu</cite> <span class="says">says:</span> </div>
<div class="comment-meta commentmetadata"><a href="http://syswip.com/wishbone-verification-ip/comment-page-1#comment-571">February 8, 2011 at 4:06 pm</a></div>
<p>Hello,</p>
<p>Good job, this is very helpfull.</p>
<p>I got an error with your slave interface asserting “ack_o” and “rty_o” during the same cycle.</p>
<p>(this is not allowed : rule 3.45) </p>
<p>A suggested correction in wshsb_s.sv line 166:</p>
<p>end else if((this.rtyNum != rtyCnt) && (this.tr.address == this.rtyAddr)) begin<br />
this.ifc.cb_n.rty_o <= 1'b1;<br />
this.ifc.cb_n.ack_o <= 1'b0;<br />
rtyCnt++;<br />
end else begin</p>
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<li class="comment byuser comment-author-syswipadmin bypostauthor odd alt thread-odd thread-alt depth-1" id="li-comment-572">
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<cite class="fn">Tiksan</cite> <span class="says">says:</span> </div>
<div class="comment-meta commentmetadata"><a href="http://syswip.com/wishbone-verification-ip/comment-page-1#comment-572">February 11, 2011 at 2:19 pm</a></div>
<p>Good catch Mathieu. Thank you very much.</p>
<p>Your correction should work(but I did not try yet).<br />
And the same correction can be applied for err_o signal generation as well.</p>
<p>Best Regards,<br />
Tiksan</p>
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<li><a rel="nofollow" title="Download i2c_vip.zip" href="http://syswip.com/download/i2c_vip.zip">I2C Verification IP</a> (2,393)</li>
<li><a rel="nofollow" title="Download apb_vip.zip" href="http://syswip.com/download/apb_vip.zip">APB Verification IP</a> (1,978)</li>
<li><a rel="nofollow" title="Download spi_vip.zip" href="http://syswip.com/download/spi_vip.zip">SPI Verification IP</a> (1,741)</li>
<li><a rel="nofollow" title="Download axi4lite_vip.zip" href="http://syswip.com/download/axi4lite_vip.zip">AXI4-Lite Verification IP</a> (1,237)</li>
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<li><a rel="nofollow" title="Download mdio_vip.zip" href="http://syswip.com/download/mdio_vip.zip">MDIO Verification IP</a> (741)</li>
<li><a rel="nofollow" title="Download avalonst_vip.zip" href="http://syswip.com/download/avalonst_vip.zip">AVALON-ST Verification IP</a> (585)</li>
<li><a rel="nofollow" title="Download can_vip.zip" href="http://syswip.com/download/can_vip.zip">CAN Verification IP</a> (218)</li>
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<li><a href="http://chip101.com" target="_blank">Chip101</a></li>
<li><a href="http://www.coolverification.com" target="_blank">Coolverification</a></li>
<li><a href="http://digitalelectronics.blogspot.com" target="_blank">Digitalelectronics blogspot</a></li>
<li><a href="http://intelligentdv.com" target="_blank">Intelligentdv</a></li>
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<li><a href="http://www.thinkverification.com" target="_blank">Thinkverification</a></li>
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<li class="cat-item cat-item-4"><a href="http://syswip.com/category/general" title="View all posts filed under General">General</a>
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<li class="cat-item cat-item-5"><a href="http://syswip.com/category/systemverilog-verification-environment" title="SystemVerilog Verification Environment">SystemVerilog Verification Environment</a>
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<li class="cat-item cat-item-6"><a href="http://syswip.com/category/systemverilog-verification-ip" title="Open Source free SystemVerilog Verification IP">SystemVerilog Verification IP</a>
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<li class="cat-item cat-item-12"><a href="http://syswip.com/category/systemverilog-verification-ip/altera-interface-verification-ip" title="Free SystemVerilog Verification IP for master and slave devices with Altera Avalon Interface">Altera Interface Verification IP</a>
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<li class="cat-item cat-item-7"><a href="http://syswip.com/category/systemverilog-verification-ip/amba-verification-ip" title="Free SystemVerilog Verification IP for AMBA APB, AHB, AXI, AXI4-Lite, BFM, master and slave devices.">AMBA Verification IP</a>
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<li class="cat-item cat-item-14"><a href="http://syswip.com/category/systemverilog-verification-ip/can-bus-systemverilog-verification-ip" title="Free SystemVerilog Verification IP for CAN Controller Area devices.">CAN-Bus Verification IP</a>
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<li class="cat-item cat-item-9"><a href="http://syswip.com/category/systemverilog-verification-ip/i2c-systemverilog-verification-ip" title="Free SystemVerilog Verification IP for I2C master and slave devices.">I2C Verification IP</a>
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<li class="cat-item cat-item-13"><a href="http://syswip.com/category/systemverilog-verification-ip/mdio-verification-ip" title="Free SystemVerilog Verification IP for MDIO serial bus, BFM, master and slave devices.">MDIO Verification IP</a>
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<li class="cat-item cat-item-10"><a href="http://syswip.com/category/systemverilog-verification-ip/spi-systemverilog-verification-ip" title="Free SystemVerilog Verification IP for SPI Serial Peripheral Interface master and slave devices.">SPI Verification IP</a>
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<li class="cat-item cat-item-11"><a href="http://syswip.com/category/systemverilog-verification-ip/wishbone-bus-verification-ip" title="Free SystemVerilog Verification IP for master and slave devices with Wishbone open source hardware computer bus">Wishbone bus Verification IP</a>
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