Subversion Repositories core1990_interlaken

\addcontentsline{toc}{section}{References}
\begin{thebibliography}{9}
 
%Introduction
\bibitem{Wikipedia_protocol}
	Wikipedia,
	\textit{"Communication protocol"}
	[On-line] Available:
	\url{https://en.wikipedia.org/wiki/Communication_protocol} [Apr. 03, 2018]
 
\bibitem{CERN}
	CERN official website,
	\textit{"Acceleration science"}
	[On-line] Available:
	\url{http://cern.ch} [Apr. 03, 2018]
 
%Structure of communication protocols
\bibitem{OSImodel}
	Tech-faq,
	\textit{"The OSI Model - What It Is; Why It Matters; Why It Doesn't Matter."}
	[On-line] Available:
	\url{http://www.tech-faq.com/osi-model.html} [Mar. 27, 2018]
 
\bibitem{EthernetPHY}
	Truechip,
	\textit{"Exploring Forward Error Correction Trends in Ethernet"}
	[On-line] Available:
	\url{http://www.truechip.net/articles-details/exploring-forward-error-correction-trends-in-ethernet/1909580257} [Mar. 28, 2018]
 
\bibitem{OSI_IP/TCP/UDP}
	Amar Shekar,
	\textit{"OSI Model And 7 Layers Of OSI Model Explained"}
	[On-line] Available:
	\url{https://fossbytes.com/osi-model-7-layers-osi-model-explained/7} [Apr. 19, 2018]
 
\bibitem{Framing}
	Eli Bendersky,
	\textit{"Framing in serial communications"}
	[on-line]. Available:\\
	\url{https://eli.thegreenplace.net/2009/08/12/framing-in-serial-communications/} [Feb. 14, 2018]
 
\bibitem{InterlakenProtocol}
	Cortina Systems Inc. and Cisco Systems Inc.
	\textit{"Interlaken	Protocol Definition"}
	[On-line] Available:
	\url{http://www.interlakenalliance.com/Interlaken_Protocol_Definition_v1.2.pdf} [Feb. 09, 2018]
 
\bibitem{SerialLiteIII_MainPage}
	Altera,
	\textit{"Intel® FPGA SerialLite III Streaming IP"}
	[on-line] Available:
	\url{https://www.altera.com/products/intellectual-property/ip/interface-protocols/m-alt-seriallite3.html} [Mar. 29, 2018]
 
\bibitem{CRCLB}
	Lammert Bies,
	\textit{"Introduction to CRC calculation"}
	[On-line] Available:
	\url{https://www.lammertbies.nl/comm/info/crc-calculation.html} [Feb. 08, 2018]
 
\bibitem{CRC1}
	Joleen Charles,
	\textit{"Cyclic Redundancy Check CRC Chapter 4"}
	[On-line] Available:
	\url{http://slideplayer.com/slide/8190698/} [Feb. 14, 2018]
 
\bibitem{turbocode}
	Dr. Sylvie Kerouédan, Dr. Claude Berrou,
	\textit{"Turbo code"}
	[On-line] Available:
	\url{http://www.scholarpedia.org/article/Turbo_code} [Feb. 14, 2018]
 
\bibitem{Gearbox}
	Louis E. Frenzel,
	\textit{"Gearbox operations"}
	[On-line] Available:
	\url{https://books.google.nl/books?id=wnGDBAAAQBAJ}  P.26 [Feb. 12, 2018]
 
%Requirements
\bibitem{FlowControl}
	TutorialsPoint,
	\textit{"Flow Control"}
	[On-line] Available:
	\url{https://www.tutorialspoint.com/data_communication_computer_network/data_link_control_and_protocols.htm} [Mar. 29, 2018]	
 
\bibitem{Bonding_Image}
	Sunsik Roh,
	\textit{"Design of Out-of-Band Protocols to Transmit UHDTV Contents in the CATV Network"}
	[On-line] Available:
	\url{http://file.scirp.org/Html/3-9701557_19481.htm} [Feb. 14, 2018]
 
\bibitem{Bonding_Altera}
	Altera,
	\textit{"Using FPGA-Based Channel Bonding for HDTV Over DSL"}
	[On-line] Available:	
	\url{https://www.altera.co.jp/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp-01053-using-fpga-based-channel-bonding-for-hdtv-over-dsl.pdf} [Mar. 21, 2018]
 
%Encoding references
\bibitem{8b10b}
	Knowledge Transfer,
	\textit{"8b/10b encoding"}
	[On-line] Available:
	\url{www.knowledgetransfer.net/dictionary/Storage/en/8b10b_encoding.htm} [Feb. 15, 2018]
 
\bibitem{scrambler}
	M. Moussavi. (5 dec. 2011)
	\textit{"Data Communication and Networking: A Practical Approach"}
	[on-line]. Available: \url{https://books.google.nl/books?id=gX8KAAAAQBAJ}. [Feb. 07, 2018]
	Cengage Learning, 5 dec. 2011
 
\bibitem{NIcoding}
	National Instruments.
	\textit{"High-Speed Serial Explained"}
	[On-line] Available: \url{ftp://ftp.ni.com/evaluation/HighSpeedSerial_WP_Final.pdf} [Feb. 07, 2018]
 
\bibitem{6466header}
	Marek Hajduczenia,
	\textit{"64b/66b line code"}
	[On-line] Available:
	\url{http://www.ieee802.org/3/bn/public/mar13/hajduczenia_3bn_04_0313.pdf} [Feb. 16, 2018]
 
\bibitem{PCIE}
  Intel.
  \textit{PHY Interface for the PCI Express, SATA, USB 3.1, DisplayPort and Converged IO Architectures}
  [On-line] Available: \url{https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/phy-interface-pci-express-sata-usb30-architectures-3.1.pdf} P.124 [Feb. 07, 2018]
 
\bibitem{USB3.1}
  Synopsys.
  \textit{"USB 3.1: Physical, Link, and Protocol Layer Changes"}
  [On-line] Available: \url{https://www.synopsys.com/designware-ip/technical-bulletin/protocol-layer-changes.html} [Feb. 07, 2018]
 
\bibitem{256b/257b}
	Roy Cideciyan (IBM),
	\textit{"256b/257b Transcoding for 100 Gb/s Backplane and Copper Cable"}
	[On-line] Available:
	\url{http://www.ieee802.org/3/100GNGOPTX/public/mar12/interim/cideciyan_01_0312_NG100GOPTX.pdf} [Feb. 16, 2018]
 
\bibitem{FibreChannel_Encoding}
	Craig W. Carlson, QLogic Corporation,
	\textit{"Gen 6 FibreChannel	What You Need to Know "}	
	[On-line] Available:
	\url{http://www.snia.org/sites/default/orig/DSI2014/presentations/StorPlumb/CraigCarlson_Gen_6_Fibre_Channel_v02.pdf} (Slide 14) [Mar. 29, 2018]
 
%Vendor dependant protocols
\bibitem{Aurora_64B66B_MainPage}
	Xilinx.
	\textit{"Aurora 64B/66B"}
	[on-line] Available:
	\url{https://www.xilinx.com/products/intellectual-property/aurora64b66b.html} [Feb. 13, 2018]
 
\bibitem{Aurora_8B10B_MainPage}
	Xilinx.
	\textit{"Aurora 8B/10B"}
	[on-line] Available:
	\url{https://www.xilinx.com/products/intellectual-property/aurora8b10b.html} [Mar. 29, 2018]
 
\bibitem{Aurora_64B66B_IpCore}
	Xilinx,
	\textit{"Aurora 64B/66B v11.2 LogiCORE IP Product Guide"}
	[on-line] Available:
	\url{https://www.xilinx.com/support/documentation/ip_documentation/aurora_64b66b/v11_2/pg074-aurora-64b66b.pdf} [Feb. 13, 2018]
 
\bibitem{SerialLiteIII_IpCore}
	Altera,
	\textit{"Intel FPGA SerialLite III Streaming IP Core User Guide"}
	[on-line] Available:
	\url{https://www.altera.com/documentation/jbz1470383208039.html} [Feb. 16, 2018]
 
\bibitem{LiteFast_IpCore}
	MicroSemi,
	\textit{"UG0701 User Guide LiteFast IP"}
	[on-line] Available:
	\url{https://www.microsemi.com/document-portal/doc_view/135971-ug0701-litefast-ip-user-guide} [Apr. 23, 2018]
%Standards references
	\bibitem{SPI4.2}
	eInfochips Ltd.
	\textit{"System Packet Interface (SPI) 4.2 IP Core"}
	[On-line] Available:
	\url{https://www.design-reuse.com/articles/18135/system-packet-interface-spi-4-2-ip-core.html} [Feb. 21, 2018]
 
 
 
\bibitem{InterlakenRS}
	Cortina Systems Inc. and Cisco Systems Inc.
	\textit{"Interlaken	Reed-Solomon Forward Error Correction Extension Protocol Definition"}
	[On-line] Available:
	\url{http://www.interlakenalliance.com/extension_v1.pdf}, Dec. 2016, [Feb. 09, 2018]
 
\bibitem{XilinxInterlaken}
	Xilinx.
	\textit{"Integrated Interlaken 150G v2.0 LogiCORE IP Product Guide"}
	[On-line] Available:
	\url{https://www.xilinx.com/support/documentation/ip_documentation/interlaken/v2_0/pg169-interlaken.pdf} [Feb. 09, 2018]
 
\bibitem{AlteraInterlaken}
	Altera.
	\textit{"Interlaken IP Core (2nd Generation) User Guide"}
	[On-line] Available:
	\url{https://www.altera.com/documentation/dsu1465510510715.html} [Feb. 09, 2018]
 
\bibitem{SATA_Specifications}
	Serial ATA International Organization,
	\textit{"Serial ATA International Organization: Serial ATA Revision 3.0 "}
	[On-line] Available:
	\url{http://www.lttconn.com/res/lttconn/pdres/201005/20100521170123066.pdf} [Apr. 09, 2018]
 
\bibitem{SATATech}
	Donovan (Don) Anderson
	\textit{"SATA Storage Technology"}
	[On-line] Available:
	\url{https://www.mindshare.com/files/ebooks/SATA%20Storage%20Technology.pdf} [Feb. 09, 2018]
 
\bibitem{SATA_E}
	Serial ATA International Organization.
	\textit{SATA Express Specification from SATA-IO in Ratification}
	[On-line] Available:
	\url{https://sata-io.org/sites/default/files/documents/SATA%20Express%20In%20Ratification_Final_Website.pdf} [Feb. 12, 2018]
 
\bibitem{SATA_E2}
	Dave Landsman, Sandisk
	\textit{AHCI and NVMe as Interfaces for SATA Express™ Devices - Overview}
	[On-line] Available:
	\url{https://sata-io.org/sites/default/files/images/NVMe_and_AHCI_as_SATA_Express_Interface_Options_Overview_final.pdf} [Feb. 12, 2018]
 
\bibitem{CPRI_Specification}
	 Ericsson AB, Huawei Technologies Co. Ltd, NEC Corporation, Alcatel Lucent, and Nokia Networks.	 
	\textit{"CPRI Specification V7.0"}
	[On-line] Available:
	\url{http://www.cpri.info/downloads/CPRI_v_7_0_2015-10-09.pdf} [Feb. 21, 2018]	
 
\bibitem{HyperTransport_Specifications}
	 HyperTransport Technology Consortium.	 
	 \textit{"HyperTransport™ I/O Link Specification Revision 3.10c"}
	 [On-line] Available:
	 \url{https://docs.wixstatic.com/ugd/071cb6_53b2dc066f2d4408b5c9368dc447e2f5.pdf} [Feb. 21, 2018]	
 
\bibitem{HTpic}
	HT consortium.
	\textit{"HyperTransport Link Specifications"}
	[On-line] Available:
	\url{https://www.hypertransport.org/ht-link-specifications} [Feb. 08, 2018]
 
\bibitem{HTIP}
	David Slogsnat, Alexander Giese, Mondrian Nüssle, Ulrich Brüning.
	\textit{"An open-source HyperTransport IP-Core"}
	[On-line] Available:
	\url{https://docs.wixstatic.com/ugd/071cb6_1d4e8365b49f4d9f8eab9b1e611ea60e.pdf} [Feb. 08, 2018]
 
\bibitem{HT3IP}
	Heiner Litz, Holger Froening, Ulrich Bruening,
	\textit{"A HyperTransport 3 Physical Layer Interface for FPGAs"}
	[On-line] Available:
	\url{https://people.ucsc.edu/~hlitz/papers/ht3phy.pdf} [Feb. 08, 2018]
 
\bibitem{FC}
	Fibre Channel Industry Association (FCIA),
	\textit{"State of the Fibre Channel Industry"}
	[On-line] Available:
	\url{http://fibrechannel.org/wp-content/uploads/2015/10/FCIA_Sol_Guide_2010_Final_v2.pdf} [Feb. 12, 2018]
 
\bibitem{FC64}
	Adrian Butter,
	\textit{"64GFC PCS/FEC Architecture Proposal for FC-FS-5"}
	[On-line] Available:
	\url{https://standards.incits.org/apps/group_public/download.php/82006/T11-2016-314v5.pdf} [Feb. 12, 2018]
 
\bibitem{FC_Xilinx}
	Xilinx,
	\textit{"LogiCORE™ IP Fibre Channel User Guide v3.5"}
	[On-line] \\ Available:
	\url{https://www.xilinx.com/support/documentation/ip_documentation/fibre_channel_ug136.pdf} [Feb. 12, 2018]	
 
\bibitem{FC_Xilinx32G}
	Xilinx,
	\textit{"32G Fibre Channel (32GFC) RS-FEC v1.0"}
	[On-line] Available:
	\url{https://www.xilinx.com/support/documentation/ip_documentation/fc32_rs_fec/v1_0/pb048-fibre-channel-32gfc-rs-fec.pdf} [Feb. 12, 2018]	
 
\bibitem{XAUI_10gea}
	10 Gigabit Ethernet Alliance (10gea),
	\textit{"XAUI interface"}
	[On-line] Available:
	\url{https://www.10gea.org/whitepapers/xaui-interface/} [Feb. 12, 2018]
 
\bibitem{XAUI_AT}
	Agilent Technologies,
	\textit{"10 Gigabit Ethernet and the XAUI interface"}
	[On-line] Available:
	\url{http://literature.cdn.keysight.com/litweb/pdf/5988-5509EN.pdf} [Feb. 12, 2018]	
 
\bibitem{HiGig}
	Altera/IntelFPGA,
	\textit{"HiGig / HiGig+ / HiGig 2"}
	[On-line] Available:
	\url{https://www.altera.com/solutions/technology/transceiver/protocols/pro-higig.html} [Feb. 16, 2018]	
 
%The Interlaken Protocol	
\bibitem{InterlakenAlliance}
	Interlaken Alliance,
	\textit{"Interlaken Alliance"}
	[On-line] Available:
	\url{http://interlakenalliance.com/} [Mar. 29, 2018]
 
\bibitem{InterlakenRecommendations}
	Interlaken Alliance,
	\textit{"Interlaken Interoperability Recommendations"}
	[On-line] Available:
	\url{http://www.interlakenalliance.com/interlaken-interoperability-recommendations-v1.10.pdf} [Apr. 03, 2018] 
 
%Hardware part
\bibitem{VC707}
	Xilinx.
	\textit{"VC707 Evaluation Board for the Virtex-7 FPGA - User Guide"}
	[On-line] Available:
	\url{https://www.xilinx.com/support/documentation/boards_and_kits/vc707/ug885_VC707_Eval_Bd.pdf} [Feb. 19, 2018]
 
\bibitem{GTXT}
	Xilinx.
	\textit{"7 Series FPGAs GTX/GTH Transceivers - User Guide"}
	[On-line] Available:
	\url{https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf} [Feb. 19, 2018]
 
\bibitem{VC707_Schematic}
	Xilinx.
	\textit{"VC707 EVALUATION PLATFORM HW-V7-VC707 (XC7VX485T-FF1761)"}
	[On-Line] Available:
	\url{https://www.xilinx.com/support/documentation/boards_and_kits/vc707_Schematic_xtp135_rev1_0.pdf} [Feb. 19, 2018]
 
%Traditional CERN Protocols
	\bibitem{S-Link}
	Erik van der Bij,
	\textit{"S-Link Overview"}
	[On-line] Available:
	\url{http://hsi.web.cern.ch/HSI/s-link/introduc/overview.htm} [Feb. 08, 2018]
 
\bibitem{GBT}
	S. Baron, J.P. Cachemiche, F. Marin, P. Moreira, C. Soos,
	\textit{"Implementing the GBT data transmission protocol in FPGAs"}
	[On-line] Available:
	\url{https://cds.cern.ch/record/1236361/files/p631.pdf} [July. 09, 2018]
 
\bibitem{GBT_LP}
	A. Marchioro, P. Moreira,
	\textit{"Low Power GBT"}
	[On-line] Available:
	\url{https://indico.cern.ch/event/153564/contributions/1397870/attachments/161703/228199/Marchioro_LP_GBT__FNAL_Nov_2011.pptx} [July. 09, 2018]
 
\bibitem{FELIX}
	J. Anderson, K. Bauer, A. Borga, H. Boterenbrood, H. Chen, K. Chen,G. Drake, M.Dönszelmann, D. Francis, D. Guest, B. Gorini, M. Joos, F. Lanni, G. Lehmann Miotto, L. Levinson, J. Narevicius, W. Panduro Vazquez, A. Roich, S. Ryu, F. Schreuder, J. Schumacher, W. Vandelli, J. Vermeulen, D. Whiteson, W. Wu and J. Zhang,
	\textit{"FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework"}
	[On-line] Available:
	\url{https://cds.cern.ch/record/2229597/files/ATL-DAQ-PROC-2016-022.pdf} [July. 09, 2018]
 
\end{thebibliography}
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