Subversion Repositories core1990_interlaken

\section{Core1990}
Core1990 is a point-to-point communication protocol using the royalty-free Interlaken protocol as it's foundation. It is designed by engineers and students of the Electronics Department of Nikhef (Amsterdam, The Netherlands) with large experiments at CERN (e.g. ATLAS) in mind. \\
The development of Core1990 was intended to publish an open source protocol providing high throughput with a small percentage of overhead. Certain features like flow control and error detection are included.
\begin{figure}[H]
	\centering
	\includegraphics[width=.7\textwidth]{Core1990_logo.jpg}	
	\caption{Core1990 logo}
	\label{fig:Core1990_logo}
\end{figure} 
 
\subsection{Features}
	Core1990 is packet with a lot of features providing data integrity and detection of errors while transmitting. These features are designed to be compliant with those featured in the interlaken protocol definition. 
 
	\begin{itemize}
		\item Lane rate transceiver dependent
		\item Support framing consistent with the Interlaken Protocol Definition
		\item Generates CRC-24 and CRC-32 for error checking
		\item 58-bit independent synchronous scrambler
		\item 64b/67b encoding
		\item About 90\% bandwidth efficiency possible (depends on user configuration)
		\item Self-synchronizing links
		\item Flow control
	\end{itemize}
 
\newpage
 
\subsection{Obtaining and building Core 1990}
	Implementing the core in a design can be done easily by using the files provided with core1990.
	The complete process of obtaining and building Core1990 will be described including which files are required and should be included. The project has been designed in Xilinx Vivado 16.4 but should be compatible with other versions. The correct configuration of the ip cores will also be mentioned to ensure behavior as expected.
 
	The complete project can be downloaded through the download link on the OpenCores site itself or through SVN. For OpenCores the link is \href{https://opencores.org/project/core1990_interlaken}{https://opencores.org/project/core1990\\\_interlaken} and the SVN links is \href{https://opencores.org/ocsvn/core1990_interlaken/core1990_interlaken/trunk}{https://opencores.org/ocsvn/core1990\_interlaken/core1990\\\_interlaken/trunk} in case this is preferred.\\
 
	 \begin{forest}
	 	pic dir tree,
	 	where level=0{}{% folder icons by default; override using file for file icons
	 		directory,
	 	},
	 	[Core1990
		 	[constraints]
		 	[scripts]
		 	[simulation]
		 	[sources
			 	[Interlaken\_Interface.vhd, file, label=right: \small{The main file}]
			 	[ip\_cores
				 	[clk\_40MHz.xci, file]
				 	[RX\_FIFO.xci, file]
				 	[Transceiver\_10g\_64b67b.xci, file]
				 	[TX\_FIFO.xci, file] ]
			 	[CRC
				 	[crc-24.vhd,file]
				 	[crc-32.vhd, file] ]
			 	[Receiver
				 	[interlaken\_receiver.vhd,file]
				 	[decoder.vhd, file]
				 	[deframing\_burst.vhd, file]
				 	[deframing\_meta.vhd, file]
				 	[descrambler.vhd, file] ] 
			 	[Transmitter
			 		[interlaken\_transmitter.vhd,file]
			 		[encoder.vhd, file]
			 		[framing\_burst.vhd, file]
			 		[framing\_meta.vhd, file]
			 		[scrambler.vhd, file] ]
	 		] 
	 	]
	 \end{forest}
 
	The directory tree depicts the file structure in the sources folder. This should contain several files to configure the ip cores, a folder containing two crc error detection modules, a receiver and transmitter folder containing the module files. A main file is included in the folder that is meant for the top level connecting all modules correctly to each other.
 
	Besides these files there are also three different folders. One contains the constraints which are responsible for connecting the physical pins to the signals in the package and providing clock information to the fitter of the design. Another folder contains several scripts to build the project by just running a single script. Another script will be able to generate testbenches on request of the user and a script generates the implementation of the design. The simulation folder contains a lot of testbenches used to simulate all the components included in the design.\\
 
	\begin{forest}
		pic dir tree,
		where level=0{}{% folder icons by default; override using file for file icons
			directory,
		},
		[Core1990
			[constraints
				[Core1990\_Constraints.xdc, file] ]
			[scripts
				[implementation.tcl, file]
				[simulation.tcl, file]
				[vivado\_import\_virtex7.tcl, file]	]
			[simulation]
			[sources] 	
		]
	\end{forest}
 
	\vspace{1mm}
	For building the project Vivado has to be opened and the vivado\_import\_virtex7.tcl has to be executed. This can be done by changing the directory in the tcl console to the scripts folder and then giving the command 'source vivado\_import\_virtex7.tcl'. This will add the project folder to the directory tree and contains the just generated project. 
 
\newpage
\subsection{Transceiver IP Core}
	Configuring the transceiver is an essential step in setting up the core. This will describe the correct settings to use for the functional behavior of the protocol. In case the transceiver is configured in a wrong way, no data or corrupted data will arrive at the receiving side. This section will guide the user to set up the transceiver in an easy way without adjusting too many clocks, targeting the VC707 board.\\
 
	The transceiver core can be configured by browsing through a separate window that will pop up. The fist tab named GT Selection should already have the GTX as GT Type selected and the shared logic should be included in the core, not the example design.
 
	After this the second tab will provide more important options. The line rate should be set to 10 Gbps while the reference clock can be set at 125 MHz. This clock is available on the board at IO pins AH7 and AH8, REFCLK0\_Q0. Using the QPLL GTX X1Y2 can be used. Figure \ref{fig:IP_TransceiverConf1} shows the correct configuration.
 
	\begin{figure}[H]
		\centering
		\includegraphics[width=\textwidth]{IP_TransceiverConf1.png}	
		\caption{Transceiver lane rate and reference clock selection}
		\label{fig:IP_TransceiverConf1}
	\end{figure} 
 
	The encoding and clocking tab shows other important settings. For both the TX and RX, the external data width should be set at 64-bits while the internal data width is 32 bits. Encoding has to be set at 64B/67B with Internal Sequence Counter and decoding has to be set at 64B/67B. The DRP/System Clock Frequency has to be set at 40 MHz. Figure \ref{fig:IP_TransceiverConf2} shows the right settings.
 
	\begin{figure}[H]
		\centering
		\includegraphics[width=0.95\textwidth]{IP_TransceiverConf2.png}	
		\caption{Transceiver encoding and system clock selection}
		\label{fig:IP_TransceiverConf2}
	\end{figure} 
 
	The other tabs are not important and no settings should be changed in these tabs. Figure \ref{fig:IP_TransceiverConf3} shows a complete summary of the features included with the transceiver when this core will be generate. The user should have the same settings on screen. 
 
	\begin{figure}[H]
		\centering
		\includegraphics[width=0.95\textwidth]{IP_TransceiverConf3.png}	
		\caption{Transceiver summary of configuration}
		\label{fig:IP_TransceiverConf3}
	\end{figure} 
 
\newpage
 
\subsection{System Clock IP Core}
	The system clock will be generated using a 200 MHz input at IO pins E18 and E19. The frequency will be scaled down using the Xilinx Clocking Wizard which generates an IP core. This is one of the clocks that will be used by the transceiver.
 
	\begin{figure}[H]
		\centering
		\includegraphics[width=\textwidth]{IP_CLK40Conf1.png}	
		\caption{System clock setting the board interface}
		\label{fig:IP_CLK40Conf1}
	\end{figure} 
 
	The input clock is differential and this should be configured like seen in Figure \ref{fig:IP_CLK40Conf1}. The second tab contains clocking options and this core makes use of a MMCM (Mixed-Mode Clock Manager). From clocking features only Frequency synthesis and phase alignment are selected. The jitter optimization is balanced and the input frequency of the primary clock is 200MHz. The secondary clock is not important. Figure \ref{fig:IP_CLK40Conf2} shows this configuration.
 
	\begin{figure}[H]
		\centering
		\includegraphics[width=\textwidth]{IP_CLK40Conf2.png}	
		\caption{System clock setting the options}
		\label{fig:IP_CLK40Conf2}
	\end{figure} 
 
	\begin{figure}[H]
		\centering
		\includegraphics[width=\textwidth]{IP_CLK40Conf3.png}	
		\caption{System clock configuring the output clock}
		\label{fig:IP_CLK40Conf3}
	\end{figure} 
 
	Only one output clock is required so this one will be selected with a 40MHz output. The duty cycle should remain 50\% which can be seen in Figure \ref{fig:IP_CLK40Conf3}. From the optional outputs only the reset and locked pins are required.
 
	The summary tab give an overview that contains the same information and values as depicted in Figure \ref{fig:IP_CLK40Conf4}. When another value is noted in the summary, there is a chance the clock won't be of the same frequency.
 
	\begin{figure}[H]
		\centering
		\includegraphics[width=\textwidth]{IP_CLK40Conf4.png}	
		\caption{System clock summary of configuration}
		\label{fig:IP_CLK40Conf4}
	\end{figure} 
 
	\newpage
 
\subsection{FIFO IP Cores}
 
\subsection{Simulating the core}
	Simulation of the core1990 protocol can easily be configure by running the simulation script. This can be done by browsing to the scripts folder again and running the tcl command 'source simulation.tcl'. After this a short explanation of the command this script accepts should appear. For example if the user would like to simulate the decoder, this can be done by giving the command 'simulate decoder' in the tcl console. \\
 
	If the link doesn't behave as expected or is malfunctioning, the situation can be analyzed in simulation. This makes locating the error easier. 
 
\subsection{Example design}
	During the design stage of Core1990 multiple tests have been run to inspect how the link behaves, whether the correct data arrives or how robust the link itself is. These tests have been performed by implementing a data generator connected to the Core1990 inputs. A VIO (Virtual Input/Output) is used to control the length of bursts and an ILA (Integrated Logic Analyzer) is used to sample the input and output data (ChipScope). The input data will be pipelined for alignment between the two. This will make it easier to detect errors and ensure data integrity.\\
 
	\begin{forest}
		pic dir tree,
		where level=0{}{% folder icons by default; override using file for file icons
			directory,
		},
		[Core1990
			[constraints]
			[scripts]
			[simulation]
			[sources
				[ip\_cores
					[ILA.xci, file]
					[vio.xci, file] ]
				[tests
					[Core1990\_Test.vhd, file]
					[data\_generator.vhd, file] 
					[pipeline.vhd, file] ]	] ]
	\end{forest}
 
	\vspace{1mm}
	The additional IP cores and VHDL components are all included in the Core1990\_Test.vhd file. This top level only requires two clocks to run, two differential signals for RX and TX are defined and a valid signal is noted as an output and connected to an external led.		
 
	\newpage