OpenCores
URL https://opencores.org/ocsvn/core_arm/core_arm/trunk

Subversion Repositories core_arm

[/] [core_arm/] [trunk/] [soft/] [sim/] [testcache.c] - Rev 4

Compare with Previous | Blame | View Log

#include <gendc.h>
 
int
main (argc, argv)
     int argc;
     char **argv;
{
 
  int size_kb = 64;
  int nr_sets = 2;
  int size_tline = 4;
  data_cache *c = gendc_create(size_kb,nr_sets,size_tline);
  unsigned int data;
 
  if (c) {    
    gendc_read(c,0x10000,&data);
    gendc_write(c,0x10004,1);
    gendc_read(c,0x10000,&data);
    gendc_read(c,0x10004,&data);
    gendc_read(c,0x20000,&data);
    gendc_read(c,0x20004,&data);
   }     
 
 
  return 0;
}
 
 

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.