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[/] [core_arm/] [trunk/] [syn/] [synplify/] [core.prj] - Rev 4

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source "core_files.tcl"
add_file -constraint "core.sdc"

impl -add syn

set_option -technology VIRTEX-E
set_option -part XCV1000E
set_option -package FG1156
set_option -speed_grade -6

set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler 0
set_option -resource_sharing 0
set_option -use_fsm_explorer 0
set_option -top_module "core"

set_option -frequency 45.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -modular 0
set_option -retiming 1

set_option -write_verilog 0
set_option -write_vhdl 0

set_option -write_apr_constraint 0

project -result_file "./core.edf"

set_option -compiler_compatible 0
impl -active "syn"

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