OpenCores

URL https://opencores.org/ocsvn/core_arm/core_arm/trunk

Subversion Repositories core_arm

[/] [core_arm/] [trunk/] [vhdl/] [Makefile] - Rev 4

Compare with Previous | Blame | View Log


targets          = sim

sim_target       =  
sim_files        = 
sim_hostcompile  = 
sim_subdirs      = mem/cache/c_model peripherals/mem/c_model bus/c_model

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.