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https://opencores.org/ocsvn/core_arm/core_arm/trunk
Subversion Repositories core_arm
[/] [core_arm/] [trunk/] [vsim/] [arm] - Rev 5
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onerror {resume}quietly WaveActivateNextPane {} 0add wave -noupdate -divider -height 50 IMSTGadd wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/imstg0/clkadd wave -noupdate -format Logic -label i.hold -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/imstg0/i.pstate.hold_r.holdadd wave -noupdate -format Logic -label i.nextinsn_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/imstg0/i.pstate.nextinsn_vadd wave -noupdate -format Logic -label i.flush_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/imstg0/i.flush_vadd wave -noupdate -divider outadd wave -noupdate -format Literal -label o.tofe_addrphy_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/imstg0/o.tofe_addrphy_vadd wave -noupdate -divider branchadd wave -noupdate -format Logic -label i.branch_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/imstg0/i.branch_vadd wave -noupdate -format Literal -label i.addrvir_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/imstg0/i.addrvir_vadd wave -noupdate -divider { }add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/imstg0/rstadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/imstg0/iadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/imstg0/oadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/imstg0/radd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/imstg0/cadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/imstg0/rdbgadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/imstg0/cdbgadd wave -noupdate -divider -height 50 FESTGadd wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/festg0/clkadd wave -noupdate -format Logic -label i.hold -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/festg0/i.pstate.hold_r.holdadd wave -noupdate -format Logic -label i.nextinsn_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/festg0/i.pstate.nextinsn_vadd wave -noupdate -format Logic -label i.flush_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/festg0/i.flush_vadd wave -noupdate -divider icacheadd wave -noupdate -format Literal -label ico.data -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/festg0/i.ico.dat_line_v.dataadd wave -noupdate -format Logic -label ico.mstrobe -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/festg0/i.ico.mstrobeadd wave -noupdate -format Literal -label ici.pc_r -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/festg0/o.ici.pc_radd wave -noupdate -format Logic -label ici.annul -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/festg0/o.ici.annuladd wave -noupdate -divider outadd wave -noupdate -format Literal -label .tode_insn_r -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/festg0/o.tode_insn_radd wave -noupdate -divider { }add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/festg0/rstadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/festg0/iadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/festg0/oadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/festg0/radd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/festg0/cadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/festg0/rdbgadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/festg0/cdbgadd wave -noupdate -divider -height 50 DESTGadd wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/destg0/clkadd wave -noupdate -format Logic -label i.hold -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/destg0/i.pstate.hold_r.holdadd wave -noupdate -format Logic -label i.nextinsn_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/destg0/i.pstate.nextinsn_vadd wave -noupdate -format Logic -label i.flush_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/destg0/i.flush_vadd wave -noupdate -divider outadd wave -noupdate -format Literal -label o.todr_insn_r -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/destg0/o.todr_insn_radd wave -noupdate -divider { }add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/destg0/rstadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/destg0/iadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/destg0/oadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/destg0/radd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/destg0/cadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/destg0/rdbgadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/destg0/cdbgadd wave -noupdate -divider -height 50 DRSTGadd wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/clkadd wave -noupdate -format Logic -label i.hold -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/i.pstate.hold_r.holdadd wave -noupdate -format Logic -label i.flush_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/i.flush_vadd wave -noupdate -format Literal -label r.pc_8 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/i.fromde_insn_r.insn.pc_8add wave -noupdate -format Literal -label r.decinsn -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/i.fromde_insn_r.insn.decinsnadd wave -noupdate -format Logic -label o.nextinsn_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/o.nextinsn_vadd wave -noupdate -divider cmdadd wave -noupdate -format Literal -label r.cnt -radix decimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/r.cntadd wave -noupdate -format Logic -label i.fromrr_nextmicro_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/i.fromrr_nextmicro_vadd wave -noupdate -format Literal -label t.ctrli -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cdbg.dbg.ctrliadd wave -noupdate -format Literal -label t.ctrlo -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cdbg.dbg.ctrloadd wave -noupdate -format Literal -label t.pctrl -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cdbg.dbg.pctrladd wave -noupdate -divider {micro out}add wave -noupdate -format Logic -label .r1_valid -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/o.torr_micro_v.r1_validadd wave -noupdate -format Literal -label .r1 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/o.torr_micro_v.r1add wave -noupdate -format Logic -label .r2_valid -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/o.torr_micro_v.r2_validadd wave -noupdate -format Literal -label .r2 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/o.torr_micro_v.r2add wave -noupdate -format Literal -label .rd -radix decimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/o.torr_micro_v.pctrl.wr.wrop_rdadd wave -noupdate -format Logic -label .rd_valid -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/o.torr_micro_v.pctrl.wr.wrop_rdvalidadd wave -noupdate -format Literal -label o.torr_micro_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/o.torr_micro_vadd wave -noupdate -divider { }add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/rstadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/iadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/oadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/radd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/rdbgadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cdbgadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdaliadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdaloadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdsriadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdsroadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdldiadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdldoadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdstiadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdstoadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdlmiadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdlmoadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdsmiadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdsmoadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdswiadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdswoadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdcriadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdcroadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdcliadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdcsoadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdcsiadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdcloadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdbliadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/drstg0/cmdbloadd wave -noupdate -divider -height 50 RRSTGadd wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/clkadd wave -noupdate -format Logic -label i.hold -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/i.pstate.hold_r.holdadd wave -noupdate -format Logic -label .valid -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/r.micro.pctrl.validadd wave -noupdate -format Literal -label r.pc_8 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/r.micro.pctrl.insn.pc_8add wave -noupdate -format Literal -label r.decinsn -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/r.micro.pctrl.insn.decinsnadd wave -noupdate -format Logic -label o.todr_nextmicro_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/o.todr_nextmicro_vadd wave -noupdate -divider writeadd wave -noupdate -format Literal -label .fromwr_rd_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/i.fromwr_rd_vadd wave -noupdate -format Logic -label .fromwr_rd_valid_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/i.fromwr_rd_valid_vadd wave -noupdate -format Literal -label .fromwr_rd_data_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/i.fromwr_rd_data_vadd wave -noupdate -divider lockadd wave -noupdate -format Logic -label t.lock -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/cdbg.dbg.lockadd wave -noupdate -format Logic -label t.lock_cpsr -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/cdbg.dbg.lock_cpsradd wave -noupdate -format Logic -label t.lock_reg -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/cdbg.dbg.lock_regadd wave -noupdate -divider forwardadd wave -noupdate -format Literal -label t.fwr1b -radix binary /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/cdbg.dbg.fwr1badd wave -noupdate -format Literal -label t.fwr2b -radix binary /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/cdbg.dbg.fwr2badd wave -noupdate -format Literal -label t.fwr1i -radix decimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/cdbg.dbg.fwr1iadd wave -noupdate -format Literal -label t.fwr2i -radix decimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/cdbg.dbg.fwr2iadd wave -noupdate -format Literal -label {.rsop_op2_src fwd } -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/o.tors_pctrl_v.rs.rsop_op2_srcadd wave -noupdate -divider { registers}add wave -noupdate -format Logic -label r.r1_valid -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/r.micro.r1_validadd wave -noupdate -format Literal -label r.r1 -radix decimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/r.micro.r1add wave -noupdate -format Logic -label r.r2_valid -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/r.micro.r2_validadd wave -noupdate -format Literal -label r.r2 -radix decimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/r.micro.r2add wave -noupdate -divider outadd wave -noupdate -format Literal -label o.data1 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/o.pctrl_r.data1add wave -noupdate -format Literal -label o.data2 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/o.pctrl_r.data2add wave -noupdate -divider { }add wave -noupdate -format Literal -label r.pctrl -radix hexadecimal -expand /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/r.micro.pctrladd wave -noupdate -format Literal -label o.tors_pctrl_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/o.tors_pctrl_vadd wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/rstadd wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/clknadd wave -noupdate -format Literal -radix hexadecimal -expand /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/iadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/oadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/radd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/cadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/rdbgadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/cdbgadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/rfiadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rrstg0/rfoadd wave -noupdate -divider -height 50 RSSTGadd wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/clkadd wave -noupdate -format Logic -label i.hold -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/i.pstate.hold_r.holdadd wave -noupdate -format Logic -label i.nextinsn_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/i.pstate.nextinsn_vadd wave -noupdate -format Logic -label .valid -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/r.pctrl.validadd wave -noupdate -format Literal -label r.pc_8 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/r.pctrl.insn.pc_8add wave -noupdate -format Literal -label r.decinsn -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/r.pctrl.insn.decinsnadd wave -noupdate -divider shiefteradd wave -noupdate -format Literal -label r.rsop_styp -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/r.pctrl.rs.rsop_stypadd wave -noupdate -format Literal -label r.rsop_sdir -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/r.pctrl.rs.rsop_sdiradd wave -noupdate -format Literal -label r.data1 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/r.pctrl.data1add wave -noupdate -format Literal -label r.data2 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/r.pctrl.data2add wave -noupdate -format Logic -label i.carry -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/i.pstate.fromex_cpsr_r.ex.cadd wave -noupdate -format Literal -label t.shieftout -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/cdbg.dbg.shieftoutadd wave -noupdate -format Logic -label t.shieftcarryout -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/c.pctrl.rs.rs_shieftcarryoutadd wave -noupdate -divider outadd wave -noupdate -format Literal -label r.rsop_op1_src -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/r.pctrl.rs.rsop_op1_srcadd wave -noupdate -format Literal -label r.rsop_op2_src -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/r.pctrl.rs.rsop_op2_srcadd wave -noupdate -format Literal -label r.rsop_buf1_src -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/r.pctrl.rs.rsop_buf1_srcadd wave -noupdate -format Literal -label r.rsop_buf2_src -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/r.pctrl.rs.rsop_buf2_srcadd wave -noupdate -format Literal -label o.data1 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/o.toex_pctrl_v.data1add wave -noupdate -format Literal -label o.data2 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/o.toex_pctrl_v.data2add wave -noupdate -divider { }add wave -noupdate -format Literal -label .pctrl -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/r.pctrladd wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/rstadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/iadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/oadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/radd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/cadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/rdbgadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/rsstg0/cdbgadd wave -noupdate -divider -height 50 EXSTGadd wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/clkadd wave -noupdate -format Logic -label i.hold -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/i.pstate.hold_r.holdadd wave -noupdate -format Logic -label i.nextinsn_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/i.pstate.nextinsn_vadd wave -noupdate -format Logic -label .valid -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/r.pctrl.validadd wave -noupdate -format Literal -label r.pc_8 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/r.pctrl.insn.pc_8add wave -noupdate -format Literal -label r.decinsn -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/r.pctrl.insn.decinsnadd wave -noupdate -divider aluopadd wave -noupdate -format Literal -label r.dbgaluop -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/cdbg.dbg.dbgaluopadd wave -noupdate -format Literal -label r.data1 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/r.pctrl.data1add wave -noupdate -format Literal -label r.data2 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/r.pctrl.data2add wave -noupdate -format Literal -label t.result -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/cdbg.dbg.resultadd wave -noupdate -divider adderadd wave -noupdate -format Logic -label .add_use -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/cdbg.dbg.add_useadd wave -noupdate -format Logic -label .add_carry -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/cdbg.dbg.add_carryadd wave -noupdate -format Logic -label .add_issub -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/cdbg.dbg.add_issubadd wave -noupdate -divider cpsradd wave -noupdate -format Literal -label r.cpsr -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/r.cpsradd wave -noupdate -format Literal -label t.newcpsr -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/cdbg.dbg.newcpsradd wave -noupdate -format Logic -label r.exop_setcpsr -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/r.pctrl.ex.exop_setcpsradd wave -noupdate -divider { out}add wave -noupdate -format Literal -label r.exop_data_src -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/r.pctrl.ex.exop_data_srcadd wave -noupdate -format Literal -label o.data1 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/o.todm_pctrl_v.data1add wave -noupdate -format Literal -label o.data2 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/o.todm_pctrl_v.data2add wave -noupdate -divider Branchingadd wave -noupdate -format Logic -label o.toim_branch_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/o.toim_branch_vadd wave -noupdate -format Literal -label o.alures_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/o.alures_vadd wave -noupdate -divider { }add wave -noupdate -format Literal -label .pctrl -radix hexadecimal -expand /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/r.pctrladd wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/rstadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/iadd wave -noupdate -format Literal -radix hexadecimal -expand /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/oadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/radd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/cadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/rdbgadd wave -noupdate -format Literal -radix hexadecimal -expand /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/exstg0/cdbgadd wave -noupdate -divider -height 50 DMSTGadd wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/dmstg0/clkadd wave -noupdate -format Logic -label i.hold -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/dmstg0/i.pstate.hold_r.holdadd wave -noupdate -format Logic -label i.nextinsn_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/dmstg0/i.pstate.nextinsn_vadd wave -noupdate -format Literal -label r.pc_8 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/dmstg0/r.pctrl.insn.pc_8add wave -noupdate -format Literal -label r.decinsn -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/dmstg0/r.pctrl.insn.decinsnadd wave -noupdate -divider { }add wave -noupdate -divider { }add wave -noupdate -format Literal -label .pctrl -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/dmstg0/r.pctrladd wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/dmstg0/rstadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/dmstg0/iadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/dmstg0/oadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/dmstg0/radd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/dmstg0/cadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/dmstg0/rdbgadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/dmstg0/cdbgadd wave -noupdate -divider -height 50 MESTGadd wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/mestg0/clkadd wave -noupdate -format Logic -label i.hold -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/mestg0/i.pstate.hold_r.holdadd wave -noupdate -format Logic -label i.nextinsn_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/mestg0/i.pstate.nextinsn_vadd wave -noupdate -format Logic -label .valid -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/mestg0/r.pctrl.validadd wave -noupdate -format Logic -label .flush_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/mestg0/i.flush_vadd wave -noupdate -format Literal -label r.pc_8 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/mestg0/r.pctrl.insn.pc_8add wave -noupdate -format Literal -label r.decinsn -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/mestg0/r.pctrl.insn.decinsnadd wave -noupdate -divider load/storeadd wave -noupdate -format Logic -label r.meop_enable -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/mestg0/r.pctrl.me.meop_enableadd wave -noupdate -format Literal -label r.meop_param -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/mestg0/r.pctrl.me.meop_paramadd wave -noupdate -format Literal -label {r.addr (data1)} -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/mestg0/r.pctrl.data1add wave -noupdate -format Literal -label {r.data (dmstg)} -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/mestg0/o.dci.data_readd wave -noupdate -divider dcacheadd wave -noupdate -format Logic -label dci.annul -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/mestg0/o.dci.annuladd wave -noupdate -divider { }add wave -noupdate -format Literal -label .pctrl -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/mestg0/r.pctrladd wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/mestg0/rstadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/mestg0/iadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/mestg0/oadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/mestg0/radd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/mestg0/cadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/mestg0/rdbgadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/mestg0/cdbgadd wave -noupdate -divider -height 50 WRSTGadd wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/clkadd wave -noupdate -format Logic -label i.hold -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/i.pstate.hold_r.holdadd wave -noupdate -format Logic -label i.nextinsn_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/i.pstate.nextinsn_vadd wave -noupdate -format Logic -label .valid -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/r.pctrl.validadd wave -noupdate -format Literal -label r.pc_8 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/r.pctrl.insn.pc_8add wave -noupdate -format Literal -label r.decinsn -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/r.pctrl.insn.decinsnadd wave -noupdate -divider { }add wave -noupdate -format Literal -label r.wrop_rd -radix decimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/r.pctrl.wr.wrop_rdadd wave -noupdate -format Logic -label r.wrop_rdvalid -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/r.pctrl.wr.wrop_rdvalidadd wave -noupdate -divider Branchingadd wave -noupdate -format Logic -label o.toim_branch_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/o.toim_branch_vadd wave -noupdate -format Literal -label o.toim_branchaddr_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/o.toim_branchaddr_vadd wave -noupdate -divider {CPSR SPSR}add wave -noupdate -format Literal -label o.toex_cpsr_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/o.toex_cpsr_vadd wave -noupdate -format Logic -label o.toex_cpsrset_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/o.toex_cpsrset_vadd wave -noupdate -format Literal -label r.spsr -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/r.spsradd wave -noupdate -format Literal -label r.pctrl.ex_cpsr -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/r.pctrl.ex.ex_cpsradd wave -noupdate -divider DCACHEadd wave -noupdate -format Logic -label dco.me_mexc -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/i.dco.me_mexcadd wave -noupdate -format Literal -label dco.wr_data -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/i.dco.wr_dataadd wave -noupdate -divider { }add wave -noupdate -format Literal -label .pctrl -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/r.pctrladd wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/rstadd wave -noupdate -format Literal -radix hexadecimal -expand /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/iadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/oadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/radd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/cadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/rdbgadd wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/wrstg0/cdbgTreeUpdate [SetDefaultTree]WaveRestoreCursors {8860 ns}WaveRestoreZoom {8603 ns} {9503 ns}configure wave -namecolwidth 150configure wave -valuecolwidth 100configure wave -justifyvalue leftconfigure wave -signalnamewidth 0configure wave -snapdistance 10configure wave -datasetprefix 0
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