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URL https://opencores.org/ocsvn/core_arm/core_arm/trunk

Subversion Repositories core_arm

[/] [core_arm/] [trunk/] [vsim/] [icache] - Rev 5

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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider -height 50 ICACHE
add wave -noupdate -format Logic -label o.hold -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/o.hold
add wave -noupdate -format Literal -label r.state -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/r.state
add wave -noupdate -divider in
add wave -noupdate -format Literal -label t.pc_r -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/i.pc_r
add wave -noupdate -format Logic -label t.bra_r -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/i.bra_r
add wave -noupdate -format Logic -label i.annul -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/i.annul
add wave -noupdate -divider { }
add wave -noupdate -format Logic -label t.reqinsn -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/cdbg.dbg.reqinsn
add wave -noupdate -format Logic -label t.hit -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/cdbg.dbg.hit
add wave -noupdate -format Logic -label t.valid -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/cdbg.dbg.valid
add wave -noupdate -divider out
add wave -noupdate -format Literal -label .data -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/o.dat_line_v.data
add wave -noupdate -format Logic -label .mstrobe -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/o.mstrobe
add wave -noupdate -divider { }
add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/rst
add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/clk
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/hold
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/i
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/o
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/ctrl
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/icmo
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/icmi
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/mcio
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/mcii
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/r
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/c
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/rdbg
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/cdbg
add wave -noupdate -divider { }
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {9240 ns}
WaveRestoreZoom {8215 ns} {9953 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0

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