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URL https://opencores.org/ocsvn/core_arm/core_arm/trunk

Subversion Repositories core_arm

[/] [core_arm/] [trunk/] [vsim/] [mctrl] - Rev 4

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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider -height 50 MCTRL
add wave -noupdate -divider {Cfg registers}
add wave -noupdate -format Logic -label .psel -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/apbi.psel
add wave -noupdate -format Literal -label .paddr -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/apbi.paddr
add wave -noupdate -format Literal -label .mcfg1 -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/r.mcfg1
add wave -noupdate -format Literal -label .mcfg2 -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/r.mcfg2
add wave -noupdate -divider Amba
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/ahbsi
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/ahbso
add wave -noupdate -divider { }
add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/rst
add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/clk
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/memi
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/memo
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/apbi
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/apbo
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/pioo
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/wpo
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/sdo
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/mctrlo
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/r
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/ri
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/wrnout
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/promdata
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/sdmo
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/sdi
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/sdapbo
add wave -noupdate -divider -height 50 {SDRAM Ctrl}
add wave -noupdate -divider {CFG register}
add wave -noupdate -format Logic -label .psel -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/sd0/sdctrl/apbi.psel
add wave -noupdate -format Literal -label .paddr -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/sd0/sdctrl/apbi.paddr
add wave -noupdate -format Literal -label .cfg -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/sd0/sdctrl/r.cfg
add wave -noupdate -divider { }
add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/sd0/sdctrl/rst
add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/sd0/sdctrl/clk
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/sd0/sdctrl/sdi
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/sd0/sdctrl/sdo
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/sd0/sdctrl/apbi
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/sd0/sdctrl/apbo
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/sd0/sdctrl/wpo
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/sd0/sdctrl/sdmo
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/sd0/sdctrl/r
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/mctrl0/sd0/sdctrl/ri
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {3378 ns}
WaveRestoreZoom {6303 ns} {8719 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0

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