OpenCores
URL https://opencores.org/ocsvn/core_arm/core_arm/trunk

Subversion Repositories core_arm

[/] [core_arm/] [trunk/] [vsim/] [sctrl] - Rev 5

Go to most recent revision | Compare with Previous | Blame | View Log

onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider -height 50 {SYSCTRL Coprocessor}
add wave -noupdate -format Logic -label i.fromprdr_nextinsn_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/i.fromprdr_nextinsn_v
add wave -noupdate -divider FESTG
add wave -noupdate -format Literal -label .decinsn -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.de.insn.decinsn
add wave -noupdate -format Logic -label .valid -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.de.insn.valid
add wave -noupdate -divider lock
add wave -noupdate -format Literal -label .r1 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.regs.r1
add wave -noupdate -format Logic -label r.lock.r1 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.regslock(1)
add wave -noupdate -format Literal -label .r2 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.regs.r2
add wave -noupdate -format Logic -label r.lock.r2 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.regslock(2)
add wave -noupdate -divider DESTG
add wave -noupdate -format Literal -label r.decinsn -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.de.insn.decinsn
add wave -noupdate -format Literal -label r.cr1 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.de.insn.cr1
add wave -noupdate -format Logic -label o.busy -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/o.cpde_prdr.busy
add wave -noupdate -format Logic -label o.last -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/o.cpde_prdr.last
add wave -noupdate -format Logic -label o.accept -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/o.cpde_prdr.accept
add wave -noupdate -format Logic -label o.active -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/o.cpde_prdr.active
add wave -noupdate -divider EXSTG
add wave -noupdate -format Literal -label r.decinsn -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.ex.insn.decinsn
add wave -noupdate -format Literal -label r.cr1 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.ex.insn.cr1
add wave -noupdate -format Literal -label o.data -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/o.cpex_prrr.data
add wave -noupdate -format Logic -label o.lock -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/o.cpex_prrr.lock
add wave -noupdate -divider WRSTG
add wave -noupdate -format Literal -label i.fromprwr_data_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/i.fromprwr_data_v
add wave -noupdate -format Literal -label .decinsn -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.wr(0).insn.decinsn
add wave -noupdate -format Literal -label .cr1 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.wr(0).insn.cr1
add wave -noupdate -divider { }
add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/rst
add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/i
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/o
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/c
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/rdbg
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/cdbg
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {8860 ns}
WaveRestoreZoom {0 ns} {2588 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.