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[/] [cowgirl/] [tags/] [start/] [mux_2_1.vhdl] - Rev 4

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library ieee;
use ieee.std_logic_1164.all;
 
entity mux_2_1 is port(
	a:	in std_logic_vector(15 downto 0);
	b:	in std_logic_vector(15 downto 0);
	sel:	in std_logic;
	o:	out std_logic_vector(15 downto 0)
);
end mux_2_1;
 
architecture mux_arch of mux_2_1 is
begin
	process(sel, a, b)
	begin
		if sel = '0' then
			o <= a;
		else
			o <= b;
		end if;
	end process;
end mux_arch;

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