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[/] [cpu16/] [trunk/] [regfile8x16.v] - Rev 2
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// megafunction wizard: %RAM: 3-PORT% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: alt3pram // ============================================================ // File Name: regfile8x16.v // Megafunction Name(s): // alt3pram // // Simulation Library Files(s): // altera_mf // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition // ************************************************************ //Copyright (C) 1991-2009 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module regfile8x16 ( clock, data, rdaddress_a, rdaddress_b, wraddress, wren, qa, qb); input clock; input [15:0] data; input [2:0] rdaddress_a; input [2:0] rdaddress_b; input [2:0] wraddress; input wren; output [15:0] qa; output [15:0] qb; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri0 wren; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif wire [15:0] sub_wire0; wire [15:0] sub_wire1; wire [15:0] qa = sub_wire0[15:0]; wire [15:0] qb = sub_wire1[15:0]; alt3pram alt3pram_component ( .wren (wren), .inclock (clock), .data (data), .rdaddress_a (rdaddress_a), .wraddress (wraddress), .rdaddress_b (rdaddress_b), .qa (sub_wire0), .qb (sub_wire1) // synopsys translate_off , .aclr (), .inclocken (), .outclock (), .outclocken (), .rden_a (), .rden_b () // synopsys translate_on ); defparam alt3pram_component.indata_aclr = "OFF", alt3pram_component.indata_reg = "INCLOCK", alt3pram_component.intended_device_family = "Cyclone II", alt3pram_component.lpm_type = "alt3pram", alt3pram_component.outdata_aclr_a = "OFF", alt3pram_component.outdata_aclr_b = "OFF", alt3pram_component.outdata_reg_a = "UNREGISTERED", alt3pram_component.outdata_reg_b = "UNREGISTERED", alt3pram_component.rdaddress_aclr_a = "OFF", alt3pram_component.rdaddress_aclr_b = "OFF", alt3pram_component.rdaddress_reg_a = "INCLOCK", alt3pram_component.rdaddress_reg_b = "INCLOCK", alt3pram_component.rdcontrol_aclr_a = "OFF", alt3pram_component.rdcontrol_aclr_b = "OFF", alt3pram_component.rdcontrol_reg_a = "UNREGISTERED", alt3pram_component.rdcontrol_reg_b = "UNREGISTERED", alt3pram_component.width = 16, alt3pram_component.widthad = 3, alt3pram_component.write_aclr = "OFF", alt3pram_component.write_reg = "INCLOCK"; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" // Retrieval info: PRIVATE: CLRdata NUMERIC "0" // Retrieval info: PRIVATE: CLRqa NUMERIC "0" // Retrieval info: PRIVATE: CLRqb NUMERIC "0" // Retrieval info: PRIVATE: CLRrdaddress_a NUMERIC "0" // Retrieval info: PRIVATE: CLRrdaddress_b NUMERIC "0" // Retrieval info: PRIVATE: CLRrren_a NUMERIC "0" // Retrieval info: PRIVATE: CLRrren_b NUMERIC "0" // Retrieval info: PRIVATE: CLRwrite NUMERIC "0" // Retrieval info: PRIVATE: Clock NUMERIC "0" // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: MIFfilename STRING "" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: REGdata NUMERIC "1" // Retrieval info: PRIVATE: REGqa NUMERIC "0" // Retrieval info: PRIVATE: REGqb NUMERIC "0" // Retrieval info: PRIVATE: REGrdaddress_a NUMERIC "1" // Retrieval info: PRIVATE: REGrdaddress_b NUMERIC "1" // Retrieval info: PRIVATE: REGrren_a NUMERIC "0" // Retrieval info: PRIVATE: REGrren_b NUMERIC "0" // Retrieval info: PRIVATE: REGwrite NUMERIC "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: WidthAddr NUMERIC "3" // Retrieval info: PRIVATE: WidthData NUMERIC "16" // Retrieval info: PRIVATE: enable NUMERIC "0" // Retrieval info: PRIVATE: rden_a NUMERIC "0" // Retrieval info: PRIVATE: rden_b NUMERIC "0" // Retrieval info: CONSTANT: INDATA_ACLR STRING "OFF" // Retrieval info: CONSTANT: INDATA_REG STRING "INCLOCK" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" // Retrieval info: CONSTANT: LPM_TYPE STRING "alt3pram" // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "OFF" // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "OFF" // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" // Retrieval info: CONSTANT: RDADDRESS_ACLR_A STRING "OFF" // Retrieval info: CONSTANT: RDADDRESS_ACLR_B STRING "OFF" // Retrieval info: CONSTANT: RDADDRESS_REG_A STRING "INCLOCK" // Retrieval info: CONSTANT: RDADDRESS_REG_B STRING "INCLOCK" // Retrieval info: CONSTANT: RDCONTROL_ACLR_A STRING "OFF" // Retrieval info: CONSTANT: RDCONTROL_ACLR_B STRING "OFF" // Retrieval info: CONSTANT: RDCONTROL_REG_A STRING "UNREGISTERED" // Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "UNREGISTERED" // Retrieval info: CONSTANT: WIDTH NUMERIC "16" // Retrieval info: CONSTANT: WIDTHAD NUMERIC "3" // Retrieval info: CONSTANT: WRITE_ACLR STRING "OFF" // Retrieval info: CONSTANT: WRITE_REG STRING "INCLOCK" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] // Retrieval info: USED_PORT: qa 0 0 16 0 OUTPUT NODEFVAL qa[15..0] // Retrieval info: USED_PORT: qb 0 0 16 0 OUTPUT NODEFVAL qb[15..0] // Retrieval info: USED_PORT: rdaddress_a 0 0 3 0 INPUT NODEFVAL rdaddress_a[2..0] // Retrieval info: USED_PORT: rdaddress_b 0 0 3 0 INPUT NODEFVAL rdaddress_b[2..0] // Retrieval info: USED_PORT: wraddress 0 0 3 0 INPUT NODEFVAL wraddress[2..0] // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND wren // Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 // Retrieval info: CONNECT: qa 0 0 16 0 @qa 0 0 16 0 // Retrieval info: CONNECT: qb 0 0 16 0 @qb 0 0 16 0 // Retrieval info: CONNECT: @wraddress 0 0 3 0 wraddress 0 0 3 0 // Retrieval info: CONNECT: @rdaddress_a 0 0 3 0 rdaddress_a 0 0 3 0 // Retrieval info: CONNECT: @rdaddress_b 0 0 3 0 rdaddress_b 0 0 3 0 // Retrieval info: CONNECT: @wren 0 0 0 0 wren 0 0 0 0 // Retrieval info: CONNECT: @inclock 0 0 0 0 clock 0 0 0 0 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: GEN_FILE: TYPE_NORMAL regfile8x16.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL regfile8x16.inc TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL regfile8x16.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL regfile8x16.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL regfile8x16_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL regfile8x16_bb.v TRUE // Retrieval info: LIB_FILE: altera_mf