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-- VHDL Entity R6502_TC.FSM_NMI.symbol
--
-- Created:
--          by - eda.UNKNOWN (TEST)
--          at - 21:30:26 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY FSM_NMI IS
   PORT( 
      clk_clk_i   : IN     std_logic;
      fetch_i     : IN     std_logic;
      nmi_n_i     : IN     std_logic;
      rst_rst_n_i : IN     std_logic;
      nmi_o       : OUT    std_logic
   );
 
-- Declarations
 
END FSM_NMI ;
 
-- Jens-D. Gutschmidt     Project:  R6502_TC  
 
-- scantara2003@yahoo.de                      
 
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG                                                                                     
 
--                                                                                                                                             
 
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by   
 
-- the Free Software Foundation, either version 3 of the License, or any later version.                                                        
 
--                                                                                                                                             
 
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of              
 
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.                                  
 
--                                                                                                                                             
 
-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.     
 
--                                                                                                                                             
 
-- CVS Revisins History                                                                                                                        
 
--                                                                                                                                             
 
-- $Log: not supported by cvs2svn $                                                                                                                            
 
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-- Title:  FSM for NMI  
 
-- Path:  R6502_TC/FSM_NMI/fsm  
 
-- Edited:  by eda on 03 Jan 2009  
 
--
-- VHDL Architecture R6502_TC.FSM_NMI.fsm
--
-- Created:
--          by - eda.UNKNOWN (TEST)
--          at - 21:30:26 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ARCHITECTURE fsm OF FSM_NMI IS
 
   TYPE STATE_TYPE IS (
      idle,
      idle1,
      idle2,
      IMP
   );
 
   -- State vector declaration
   ATTRIBUTE state_vector : string;
   ATTRIBUTE state_vector OF fsm : ARCHITECTURE IS "current_state";
 
   -- Declare current and next state signals
   SIGNAL current_state : STATE_TYPE;
   SIGNAL next_state : STATE_TYPE;
 
   -- Declare any pre-registered internal signals
   SIGNAL nmi_o_cld : std_logic ;
 
BEGIN
 
   -----------------------------------------------------------------
   clocked_proc : PROCESS ( 
      clk_clk_i,
      rst_rst_n_i
   )
   -----------------------------------------------------------------
   BEGIN
      IF (rst_rst_n_i = '0') THEN
         current_state <= idle;
         -- Default Reset Values
         nmi_o_cld <= '0';
      ELSIF (clk_clk_i'EVENT AND clk_clk_i = '1') THEN
         current_state <= next_state;
         -- Default Assignment To Internals
         nmi_o_cld <= '0';
 
         -- Combined Actions
         CASE current_state IS
            WHEN IMP => 
               nmi_o_cld <= '1';
            WHEN OTHERS =>
               NULL;
         END CASE;
      END IF;
   END PROCESS clocked_proc;
 
   -----------------------------------------------------------------
   nextstate_proc : PROCESS ( 
      current_state,
      fetch_i,
      nmi_n_i
   )
   -----------------------------------------------------------------
   BEGIN
      CASE current_state IS
         WHEN idle => 
            IF (nmi_n_i = '1') THEN 
               next_state <= idle1;
            ELSE
               next_state <= idle;
            END IF;
         WHEN idle1 => 
            IF (nmi_n_i = '0') THEN 
               next_state <= idle2;
            ELSE
               next_state <= idle1;
            END IF;
         WHEN idle2 => 
            IF (nmi_n_i = '0') THEN 
               next_state <= IMP;
            ELSE
               next_state <= idle;
            END IF;
         WHEN IMP => 
            IF (fetch_i = '1') THEN 
               next_state <= idle;
            ELSE
               next_state <= IMP;
            END IF;
         WHEN OTHERS =>
            next_state <= idle;
      END CASE;
   END PROCESS nextstate_proc;
 
   -- Concurrent Statements
   -- Clocked output assignments
   nmi_o <= nmi_o_cld;
END fsm;