Subversion Repositories cpu6502_true_cycle

(September 15th 2018)
- (WORKING) Performance improvements
- (WORKING) Creating test strategy for RDY signal
- (DONE) Working on reported Bugs/Requests: Branches, Interrupts, ADC/SBC
- (DONE) Verifying all interrupts
- (90%)  Finish working for Specification of cpu65C02_tc

(March 15th 2010)
- (DONE) Bug fix for wrong interrupt sequences in IRQ and NMI. Tested by
         simulation with RTI and in a real environment by customer.
- (DONE) Removed directory ./verilog_TRIAL from source.
- (DONE) Updated HTML

(February 25th 2009)
- (DONE) CORRECTED "RTI" (wrong: use of stack pointer)
- (DONE) RENAME all states of "FSM Execution Unit" for better reading
- (90%) Finish working for Specification of cpu6502_tc

(January, 4th 2009)
- (DONE) Remove unused nets, register and modules
- (85%) Finish working for Specification of cpu65C02_tc
- (DONE) Update the HDL Designer files for better viewing and 
  understanding

(August, 5th 2008)
- (DONE) Rename all port names (_i, _o, _o_i)
- (DONE) Test and verify all Op Codes
- (DONE) Optimize core for speed
- (75%) Finish working for Specification of cpu65C02_tc
- (WORKING) Create high level testbench in assembler and hardware for 
  testing all Op Codes (include accurate cycle timing)
- (WORKING) Create simulation files for Modelsim
- (WORKING) Create a simple .wlf file to demonstrate the cpu6502_tc
- Update the HDL Designer files for better viewing and understanding