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-- VHDL Entity R6502_TC.R6502_TC.symbol
--
-- Created:
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
--          at - 11:47:57 23.02.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
entity R6502_TC is
   port( 
      clk_clk_i   : in     std_logic;
      d_i         : in     std_logic_vector (7 downto 0);
      irq_n_i     : in     std_logic;
      nmi_n_i     : in     std_logic;
      rdy_i       : in     std_logic;
      rst_rst_n_i : in     std_logic;
      so_n_i      : in     std_logic;
      a_o         : out    std_logic_vector (15 downto 0);
      d_o         : out    std_logic_vector (7 downto 0);
      rd_o        : out    std_logic;
      sync_o      : out    std_logic;
      wr_o        : out    std_logic
   );
 
-- Declarations
 
end R6502_TC ;
 
-- Jens-D. Gutschmidt     Project:  R6502_TC  
-- scantara2003@yahoo.de                      
-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG                                                                                
--                                                                                                                                             
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by   
-- the Free Software Foundation, either version 3 of the License, or any later version.                                                        
--                                                                                                                                             
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of              
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.                                  
--                                                                                                                                             
-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.     
--                                                                                                                                             
-- CVS Revisins History                                                                                                                        
--                                                                                                                                             
-- $Log: not supported by cvs2svn $                                                                                                                         
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-- Title:  Top Level  
-- Path:  R6502_TC/R6502_TC/struct  
-- Edited:  by eda on 10 Feb 2009  
--
-- VHDL Architecture R6502_TC.R6502_TC.struct
--
-- Created:
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
--          at - 11:47:58 23.02.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
library R6502_TC;
 
architecture struct of R6502_TC is
 
   -- Architecture declarations
 
   -- Internal signal declarations
 
 
   -- Component Declarations
   component Core
   port (
      clk_clk_i   : in     std_logic ;
      d_i         : in     std_logic_vector (7 downto 0);
      irq_n_i     : in     std_logic ;
      nmi_n_i     : in     std_logic ;
      rdy_i       : in     std_logic ;
      rst_rst_n_i : in     std_logic ;
      so_n_i      : in     std_logic ;
      a_o         : out    std_logic_vector (15 downto 0);
      d_o         : out    std_logic_vector (7 downto 0);
      rd_o        : out    std_logic ;
      sync_o      : out    std_logic ;
      wr_o        : out    std_logic 
   );
   end component;
 
   -- Optional embedded configurations
   -- pragma synthesis_off
   for all : Core use entity R6502_TC.Core;
   -- pragma synthesis_on
 
 
begin
 
   -- Instance port mappings.
   U_0 : Core
      port map (
         clk_clk_i   => clk_clk_i,
         d_i         => d_i,
         irq_n_i     => irq_n_i,
         nmi_n_i     => nmi_n_i,
         rdy_i       => rdy_i,
         rst_rst_n_i => rst_rst_n_i,
         so_n_i      => so_n_i,
         a_o         => a_o,
         d_o         => d_o,
         rd_o        => rd_o,
         sync_o      => sync_o,
         wr_o        => wr_o
      );
 
end struct;