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<title>R65C02_TC\fsm_nmi\fsm_sm_csm</title>
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<H4>Signal Status</H4>
<TABLE><TR><TD CLASS=odd>NAME</TD><TD CLASS=even>MODE</TD><TD CLASS=odd>SCHEME</TD><TD CLASS=even>DEFAULT</TD><TD CLASS=odd>RESET</TD></TR>
<TR><TD CLASS=odd>nmi_o</TD><TD CLASS=even>out</TD><TD CLASS=odd>Clocked</TD><TD CLASS=even>'0'</TD><TD CLASS=odd>'0'</TD></TR>
</TABLE>
<H4>Generation Settings</H4>
<TABLE>
<TR><TD CLASS=odd>Machine </TD><TD CLASS=even> "csm", synchronous</TD></TR>
<TR><TD CLASS=odd>Encoding </TD><TD CLASS=even> none</TD></TR>
<TR><TD CLASS=odd>Style </TD><TD CLASS=even> case, 3 processes</TD></TR>
<TR><TD CLASS=odd>Clock</TD><TD CLASS=even> "clk_clk_i", rising</TD></TR>
<TR><TD CLASS=odd>Reset</TD><TD CLASS=even> "rst_rst_n_i", asynchronous, active low</TD></TR>
<TR><TD CLASS=odd>State variable type </TD><TD CLASS=even> [auto]</TD></TR>
<TR><TD COLSPAN=2 CLASS=odd>Default state assignment disabled</TD></TR>
<TR><TD COLSPAN=2 CLASS=odd>State actions registered on current state</TD></TR>
</TABLE>
<H4>Architecture Declarations</H4>
<pre CLASS=indent>
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<H4>Global Actions</H4>
<dir><H4>Pre Actions:</H4>
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<H4>Post Actions:</H4>
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</dir><H4>Concurrent Statements</H4>
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<H4>State Register Statements</H4>
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<H4>VHDL Process Declarations</H4>
<dir><H4>Clocked Process:</H4>
<pre CLASS=indent>
</pre>
<H4>Output Process:</H4>
<pre CLASS=indent>
</pre>
</dir><H4>Package List</H4>
<pre CLASS=indent>
<span class=K>LIBRARY</span> ieee;
<span class=K>USE</span> ieee.std_logic_1164.<span class=K>all</span>;
<span class=K>USE</span> ieee.std_logic_arith.<span class=K>all</span>;</pre>
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