Subversion Repositories cpu8080

<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
     by the Xilinx ISE software.  Any direct editing or
     changes made to this file may result in unpredictable
     behavior or data corruption.  It is strongly advised that
     users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="LIT" num="243" delta="unknown" >Logical network <arg fmt="%s" index="1">adm3a/display/inst_Mram_mem960/SPO</arg> has no load.
</msg>

<msg type="warning" file="LIT" num="395" delta="unknown" >The above <arg fmt="%s" index="1">warning</arg> message <arg fmt="%s" index="2">base_net_load_rule</arg> is repeated <arg fmt="%d" index="3">839</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="4">adm3a/display/inst_Mram_mem1100/SPO,
adm3a/display/inst_Mram_mem2100/SPO,
adm3a/display/inst_Mram_mem3100/SPO,
adm3a/display/inst_Mram_mem4100/SPO,
adm3a/display/inst_Mram_mem5100/SPO</arg>
To see the details of these <arg fmt="%s" index="5">warning</arg> messages, please use the -detail switch.
</msg>

<msg type="info" file="MapLib" num="562" delta="unknown" >No environment variables are currently set.
</msg>

<msg type="info" file="MapLib" num="535" delta="unknown" >The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
<arg fmt="%s" index="1">BUFGP symbol &quot;clock_BUFGP&quot; (output signal=clock_BUFGP),
BUFGP symbol &quot;reset_n_BUFGP&quot; (output signal=reset_n_BUFGP)</arg>
</msg>

<msg type="info" file="LIT" num="244" delta="unknown" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.
</msg>

<msg type="warning" file="LIT" num="175" delta="unknown" >Clock buffer is designated to drive clock loads. <arg fmt="%s" index="1">BUFGMUX symbol &quot;physical_group_reset_n_BUFGP/reset_n_BUFGP/BUFG&quot; (output signal=reset_n_BUFGP)</arg> has a mix of clock and non-clock loads. Some of the non-clock loads are (maximum of 5 listed):
<arg fmt="%s" index="2">Pin CLR of cpu/readmem
Pin CLR of cpu/inta
Pin CE of cpu/addr_0
Pin CE of cpu/addr_1
Pin CE of cpu/addr_2</arg>
</msg>

<msg type="warning" file="Pack" num="266" delta="unknown" >The function generator <arg fmt="%s" index="1">adm3a/display/chradr&lt;4&gt;81</arg> failed to merge with F5 multiplexer <arg fmt="%s" index="2">adm3a/display/chradr&lt;5&gt;_f5_62</arg>.  <arg fmt="%z" index="3">There is a conflict for the FXMUX.</arg>  The design will exhibit suboptimal timing.
</msg>

<msg type="warning" file="Pack" num="266" delta="unknown" >The function generator <arg fmt="%s" index="1">cpu/_mux0003_SW1</arg> failed to merge with F5 multiplexer <arg fmt="%s" index="2">cpu/_mux0003</arg>.  <arg fmt="%z" index="3">There is a conflict for the FXMUX.</arg>  The design will exhibit suboptimal timing.
</msg>

<msg type="warning" file="Pack" num="266" delta="unknown" >The function generator <arg fmt="%s" index="1">cpu/_mux0003_SW1</arg> failed to merge with F5 multiplexer <arg fmt="%s" index="2">cpu/_mux00071_f5</arg>.  <arg fmt="%z" index="3">There is a conflict for the FXMUX.</arg>  The design will exhibit suboptimal timing.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net select1/selectb/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net select1/selecta/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net select1/selectc/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net select1/selectd/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

</messages>