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<html><head><link type='text/css' href='style.css' rel='stylesheet'></head><body class='pgBgnd'>
<h3 align='center'>Equations</h3>
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</td></tr><tr><td>
********** UnMapped Logic **********
</td></tr><tr><td>
** Outputs **
</td></tr><tr><td>
FTCPE_addr0: FTCPE port map (addr(0),addr_T(0),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addr_T(0) <= ((addr(0) AND N_PZ_1066 AND NOT addrhold(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (addr(0) AND NOT pc(0) AND N_PZ_1065)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT addr(0) AND N_PZ_1066 AND addrhold(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT addr(0) AND pc(0) AND N_PZ_1065)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND addr(0) AND state(3) AND NOT state(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(4) AND state(1) AND state(0) AND _xor0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT addr(0) AND state(3) AND NOT state(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(4) AND state(1) AND state(0) AND NOT _xor0000));
</td></tr><tr><td>
FDCPE_addr1: FDCPE port map (addr(1),addr_D(1),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addr_D(1) <= ((N_PZ_1066 AND addrhold(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (pc(1) AND N_PZ_1065)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1246 AND addr(1)));
</td></tr><tr><td>
FTCPE_addr2: FTCPE port map (addr(2),addr_T(2),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addr_T(2) <= ((N_PZ_1066 AND addrhold(2) AND NOT addr(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1066 AND NOT addrhold(2) AND addr(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (pc(2) AND N_PZ_1065 AND NOT addr(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT pc(2) AND N_PZ_1065 AND addr(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND addr(2)));
</td></tr><tr><td>
FDCPE_addr3: FDCPE port map (addr(3),addr_D(3),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addr_D(3) <= ((N_PZ_1066 AND addrhold(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (pc(3) AND N_PZ_1065)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1246 AND addr(3)));
</td></tr><tr><td>
FTCPE_addr4: FTCPE port map (addr(4),addr_T(4),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addr_T(4) <= ((N_PZ_1066 AND addrhold(4) AND NOT addr(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1066 AND NOT addrhold(4) AND addr(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (pc(4) AND N_PZ_1065 AND NOT addr(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT pc(4) AND N_PZ_1065 AND addr(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND addr(4)));
</td></tr><tr><td>
FDCPE_addr5: FDCPE port map (addr(5),addr_D(5),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addr_D(5) <= ((N_PZ_1066 AND addrhold(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (pc(5) AND N_PZ_1065)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1246 AND addr(5)));
</td></tr><tr><td>
FTCPE_addr6: FTCPE port map (addr(6),addr_T(6),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addr_T(6) <= ((N_PZ_1066 AND addrhold(6) AND NOT addr(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1066 AND NOT addrhold(6) AND addr(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (pc(6) AND N_PZ_1065 AND NOT addr(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT pc(6) AND N_PZ_1065 AND addr(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND addr(6)));
</td></tr><tr><td>
FDCPE_addr7: FDCPE port map (addr(7),addr_D(7),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addr_D(7) <= ((N_PZ_1066 AND addrhold(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (pc(7) AND N_PZ_1065)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1246 AND addr(7)));
</td></tr><tr><td>
FTCPE_addr8: FTCPE port map (addr(8),addr_T(8),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addr_T(8) <= ((N_PZ_1066 AND addrhold(8) AND NOT addr(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1066 AND NOT addrhold(8) AND addr(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (pc(8) AND N_PZ_1065 AND NOT addr(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT pc(8) AND N_PZ_1065 AND addr(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND addr(8)));
</td></tr><tr><td>
FDCPE_addr9: FDCPE port map (addr(9),addr_D(9),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addr_D(9) <= ((N_PZ_1066 AND addrhold(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (pc(9) AND N_PZ_1065)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1246 AND addr(9)));
</td></tr><tr><td>
FTCPE_addr10: FTCPE port map (addr(10),addr_T(10),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addr_T(10) <= ((N_PZ_1066 AND addrhold(10) AND NOT addr(10))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1066 AND NOT addrhold(10) AND addr(10))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (pc(10) AND N_PZ_1065 AND NOT addr(10))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT pc(10) AND N_PZ_1065 AND addr(10))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND addr(10)));
</td></tr><tr><td>
FDCPE_addr11: FDCPE port map (addr(11),addr_D(11),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addr_D(11) <= ((N_PZ_1066 AND addrhold(11))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (pc(11) AND N_PZ_1065)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (addr(11) AND N_PZ_1246));
</td></tr><tr><td>
FTCPE_addr12: FTCPE port map (addr(12),addr_T(12),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addr_T(12) <= ((N_PZ_1066 AND addrhold(12) AND NOT addr(12))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1066 AND NOT addrhold(12) AND addr(12))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (pc(12) AND N_PZ_1065 AND NOT addr(12))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT pc(12) AND N_PZ_1065 AND addr(12))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND addr(12)));
</td></tr><tr><td>
FDCPE_addr13: FDCPE port map (addr(13),addr_D(13),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addr_D(13) <= ((N_PZ_1066 AND addrhold(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (pc(13) AND N_PZ_1065)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1246 AND addr(13)));
</td></tr><tr><td>
FTCPE_addr14: FTCPE port map (addr(14),addr_T(14),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addr_T(14) <= ((N_PZ_1066 AND addrhold(14) AND NOT addr(14))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1066 AND NOT addrhold(14) AND addr(14))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (pc(14) AND N_PZ_1065 AND NOT addr(14))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT pc(14) AND N_PZ_1065 AND addr(14))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND addr(14)));
</td></tr><tr><td>
FDCPE_addr15: FDCPE port map (addr(15),addr_D(15),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addr_D(15) <= ((N_PZ_1066 AND addrhold(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (pc(15) AND N_PZ_1065)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1246 AND addr(15)));
</td></tr><tr><td>
FTCPE_data0: FTCPE port map (data_I(0),data_T(0),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data_T(0) <= ((NOT reset AND state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND regfil_4_0 AND NOT data(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_4_0 AND data(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND regfil_5_0 AND NOT data(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_5_0 AND data(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND _COND_18(0) AND data(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT _COND_18(0) AND NOT data(0)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data(0) <= data_I(0) when data_OE(0) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data_OE(0) <= dataeno;
</td></tr><tr><td>
FTCPE_data1: FTCPE port map (data_I(1),data_T(1),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data_T(1) <= ((NOT reset AND state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND regfil_4_1 AND NOT data(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_4_1 AND data(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND regfil_5_1 AND NOT data(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_5_1 AND data(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND _COND_18(1) AND data(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT _COND_18(1) AND NOT data(1)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data(1) <= data_I(1) when data_OE(1) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data_OE(1) <= dataeno;
</td></tr><tr><td>
FTCPE_data2: FTCPE port map (data_I(2),data_T(2),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data_T(2) <= ((NOT reset AND state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND regfil_4_2 AND NOT data(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_4_2 AND data(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND regfil_5_2 AND NOT data(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_5_2 AND data(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND _COND_18(2) AND data(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT _COND_18(2) AND NOT data(2)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data(2) <= data_I(2) when data_OE(2) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data_OE(2) <= dataeno;
</td></tr><tr><td>
FTCPE_data3: FTCPE port map (data_I(3),data_T(3),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data_T(3) <= ((NOT reset AND state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND regfil_4_3 AND NOT data(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_4_3 AND data(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND regfil_5_3 AND NOT data(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_5_3 AND data(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND _COND_18(3) AND data(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT _COND_18(3) AND NOT data(3)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data(3) <= data_I(3) when data_OE(3) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data_OE(3) <= dataeno;
</td></tr><tr><td>
FTCPE_data4: FTCPE port map (data_I(4),data_T(4),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data_T(4) <= ((NOT reset AND state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND regfil_4_4 AND NOT data(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_4_4 AND data(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND regfil_5_4 AND NOT data(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_5_4 AND data(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND _COND_18(4) AND data(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT _COND_18(4) AND NOT data(4)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data(4) <= data_I(4) when data_OE(4) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data_OE(4) <= dataeno;
</td></tr><tr><td>
FTCPE_data5: FTCPE port map (data_I(5),data_T(5),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data_T(5) <= ((NOT reset AND state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND regfil_4_5 AND NOT data(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_4_5 AND data(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND regfil_5_5 AND NOT data(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_5_5 AND data(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND _COND_18(5) AND data(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT _COND_18(5) AND NOT data(5)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data(5) <= data_I(5) when data_OE(5) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data_OE(5) <= dataeno;
</td></tr><tr><td>
FTCPE_data6: FTCPE port map (data_I(6),data_T(6),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data_T(6) <= ((NOT reset AND state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND regfil_4_6 AND NOT data(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_4_6 AND data(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND regfil_5_6 AND NOT data(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_5_6 AND data(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND _COND_18(6) AND data(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT _COND_18(6) AND NOT data(6)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data(6) <= data_I(6) when data_OE(6) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data_OE(6) <= dataeno;
</td></tr><tr><td>
FTCPE_data7: FTCPE port map (data_I(7),data_T(7),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data_T(7) <= ((NOT reset AND state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND regfil_4_7 AND NOT data(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_4_7 AND data(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND regfil_5_7 AND NOT data(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_5_7 AND data(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND _COND_18(7) AND data(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT _COND_18(7) AND NOT data(7)));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data(7) <= data_I(7) when data_OE(7) = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;data_OE(7) <= dataeno;
</td></tr><tr><td>
FTCPE_inta: FTCPE port map (inta,inta_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;inta_T <= ((reset AND inta)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND NOT state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0) AND inta AND NOT intr)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT inta AND intr));
</td></tr><tr><td>
</td></tr><tr><td>
readio <= '0';
</td></tr><tr><td>
FDCPE_readmem: FDCPE port map (readmem,readmem_D,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;readmem_D <= NOT N_PZ_1246
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((state(3) AND state(1) AND N_PZ_1066 AND NOT N_PZ_1246 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT readmem)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(4) AND state(1) AND N_PZ_1066 AND NOT N_PZ_1246 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT readmem)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(1) AND NOT state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1246 AND readmem)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(2) AND state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1246 AND readmem)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(2) AND NOT state(1) AND NOT state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1246 AND readmem)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(4) AND NOT state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0) AND N_PZ_1246 AND readmem)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(1) AND state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1948 AND N_PZ_1246 AND readmem)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(2) AND state(4) AND NOT N_PZ_1066 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1948 AND N_PZ_1246 AND readmem));
</td></tr><tr><td>
</td></tr><tr><td>
writeio <= '0';
</td></tr><tr><td>
FTCPE_writemem: FTCPE port map (writemem,writemem_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;writemem_T <= ((reset AND writemem)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(2) AND NOT state(4) AND NOT state(1) AND NOT state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	writemem)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0) AND NOT writemem)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (state(3) AND state(2) AND state(4) AND NOT state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND writemem)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT writemem));
</td></tr><tr><td>
** Buried Nodes **
</td></tr><tr><td>
</td></tr><tr><td>
Madd__AUX_10_Mxor_Result(12)__xor0000 <= (regfil_5_7 AND regfil_4_2 AND regfil_4_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_4_0 AND regfil_4_3);
</td></tr><tr><td>
</td></tr><tr><td>
Madd__AUX_10__or0010 <= ((NOT regfil_4_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_7 AND regfil_4_2 AND regfil_4_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_4_0));
</td></tr><tr><td>
</td></tr><tr><td>
Madd__AUX_11__or0001 <= ((regfil_5_2 AND sp(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_2 AND NOT sp(2) AND N_PZ_1725)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_2 AND sp(2) AND N_PZ_1725));
</td></tr><tr><td>
</td></tr><tr><td>
Madd__AUX_11__or0006 <= ((NOT sp(7) AND N_PZ_1982)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2108 AND N_PZ_2169 AND NOT N_PZ_1982)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_2169 AND NOT sp(6) AND NOT N_PZ_1982));
</td></tr><tr><td>
</td></tr><tr><td>
Madd__AUX_11__or0008 <= ((NOT regfil_4_1 AND NOT sp(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_4_1 AND NOT N_PZ_2362)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT sp(9) AND NOT N_PZ_2362));
</td></tr><tr><td>
</td></tr><tr><td>
Madd__AUX_11__or0009 <= ((NOT regfil_4_2 AND NOT sp(10))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_4_2 AND Madd__AUX_11__or0008)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT sp(10) AND Madd__AUX_11__or0008));
</td></tr><tr><td>
</td></tr><tr><td>
Madd__AUX_11__or0010 <= ((NOT regfil_4_3 AND NOT sp(11))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_4_3 AND NOT sp(11) AND Madd__AUX_11__or0009)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_4_3 AND sp(11) AND Madd__AUX_11__or0009));
</td></tr><tr><td>
</td></tr><tr><td>
Madd__AUX_11__or0012 <= ((N_PZ_1848 AND NOT sp(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (Madd__AUX_11__or0010 AND NOT N_PZ_1929 AND NOT N_PZ_1848)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1929 AND NOT sp(12) AND NOT N_PZ_1848));
</td></tr><tr><td>
</td></tr><tr><td>
Madd__AUX_8__or0008 <= ((regfil_0_1 AND _addsub0000(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_4_1 AND regfil_0_0 AND N_PZ_1870)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_0_1 AND regfil_0_0 AND N_PZ_1870));
</td></tr><tr><td>
</td></tr><tr><td>
Madd__AUX_8__or0009 <= ((NOT regfil_0_2 AND NOT Madd__AUX_8__or0008)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_4_2 AND NOT regfil_0_2 AND N_PZ_1913)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_4_2 AND N_PZ_1913 AND NOT Madd__AUX_8__or0008)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_4_2 AND NOT regfil_0_2 AND NOT N_PZ_1913)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_4_2 AND NOT N_PZ_1913 AND NOT Madd__AUX_8__or0008));
</td></tr><tr><td>
</td></tr><tr><td>
Madd__AUX_8__or0010 <= ((NOT _addsub0000(11) AND Madd__AUX_8__or0009)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_0_3 AND _addsub0000(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__AUX_8__or0009)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_0_3 AND NOT _addsub0000(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__AUX_8__or0009));
</td></tr><tr><td>
</td></tr><tr><td>
Madd__AUX_8__or0011 <= ((NOT regfil_0_4 AND NOT _addsub0000(12))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_0_4 AND Madd__AUX_8__or0010)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT _addsub0000(12) AND Madd__AUX_8__or0010));
</td></tr><tr><td>
</td></tr><tr><td>
Madd__AUX_9__or0008 <= (NOT regfil_4_1 AND N_PZ_2057)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((NOT regfil_2_1 AND NOT N_PZ_2057)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_4_0 AND NOT Madd__addsub0001__or0006 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2057));
</td></tr><tr><td>
</td></tr><tr><td>
Madd__AUX_9__or0011 <= ((NOT regfil_2_4 AND NOT _addsub0001(12))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_2_3 AND NOT regfil_2_4 AND NOT N_PZ_2052)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_2_3 AND NOT _addsub0001(12) AND NOT N_PZ_2052)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_2_4 AND NOT _addsub0001(11) AND N_PZ_2052)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT _addsub0001(11) AND NOT _addsub0001(12) AND N_PZ_2052));
</td></tr><tr><td>
</td></tr><tr><td>
Madd__addsub0000__or0000 <= ((regfil_5_1 AND regfil_1_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_0 AND regfil_1_0 AND regfil_5_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_0 AND regfil_1_0 AND regfil_1_1));
</td></tr><tr><td>
</td></tr><tr><td>
Madd__addsub0000__or0002 <= ((NOT regfil_5_3 AND NOT regfil_1_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_3 AND N_PZ_2004)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_1_3 AND N_PZ_2004));
</td></tr><tr><td>
</td></tr><tr><td>
Madd__addsub0000__or0004 <= ((NOT regfil_5_5 AND NOT regfil_1_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_5 AND NOT regfil_1_5 AND N_PZ_2148)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_5 AND regfil_1_5 AND N_PZ_2148));
</td></tr><tr><td>
</td></tr><tr><td>
Madd__addsub0000__or0006 <= ((NOT regfil_5_7 AND NOT regfil_1_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_7 AND NOT regfil_1_7 AND N_PZ_2147)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_7 AND regfil_1_7 AND N_PZ_2147));
</td></tr><tr><td>
</td></tr><tr><td>
Madd__addsub0001__or0000 <= ((regfil_3_1 AND regfil_5_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_0 AND regfil_3_0 AND regfil_3_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_0 AND regfil_3_0 AND regfil_5_1));
</td></tr><tr><td>
</td></tr><tr><td>
Madd__addsub0001__or0006 <= ((NOT regfil_5_7 AND N_PZ_2050)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_3_7 AND NOT N_PZ_2050));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1038 <= ((aluoprb(5) AND NOT aluopra(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT aluoprb(5) AND aluopra(5)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1041 <= ((aluoprb(2) AND aluopra(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT aluoprb(2) AND NOT aluopra(2)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1043 <= ((aluoprb(1) AND NOT aluopra(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT aluoprb(1) AND aluopra(1)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1054 <= ((aluopra(4) AND NOT aluoprb(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT aluopra(4) AND aluoprb(4)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1059 <= ((aluoprb(6) AND NOT aluopra(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT aluoprb(6) AND aluopra(6)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1060 <= ((NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND regd(0)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1061 <= ((NOT reset AND state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1062 <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND N_PZ_1129));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1065 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1066 <= ((NOT reset AND state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(2) AND state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1076 <= ((aluoprb(0) AND NOT aluopra(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT aluoprb(0) AND aluopra(0)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1082 <= ((aluoprb(3) AND NOT aluopra(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT aluoprb(3) AND aluopra(3)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1092 <= ((aluoprb(7) AND NOT aluopra(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT aluoprb(7) AND aluopra(7)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1099 <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1100 <= ((N_PZ_1528)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1117 <= ((reset)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(0) AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1122 <= (regfil_5_3 AND regfil_5_0 AND regfil_5_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_5_2 AND regfil_5_4);
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1129 <= (regd(2) AND NOT regd(1) AND regd(0));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1133 <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND N_PZ_1921)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT data(5).PIN));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1141 <= ((alusel(1) AND alusel(2) AND aluopra(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND m1/Mmux__old_resi_28_I3_Result28 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/_addsub0000(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(0) AND alusel(2) AND aluoprb(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(2) AND m1/Msub__AUX_23__xor0013 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/Msub__AUX_23__xor0010)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(2) AND m1/Msub__AUX_23__xor0013 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1999)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND alusel(2) AND N_PZ_1038)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND NOT alusel(2) AND NOT m1/_addsub0000(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/_addsub0000(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(0) AND alusel(2) AND aluoprb(5) AND aluopra(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND NOT alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__old_resi_28_I3_Result28 AND m1/_addsub0000(4) AND NOT m1/_addsub0000(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND m1/Mmux__old_resi_28_I3_Result28 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Msub__AUX_23__xor0013 AND NOT m1/Msub__AUX_23__xor0010 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Msub__AUX_23__xor0007 AND NOT N_PZ_1926 AND N_PZ_2177));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1143 <= (regfil_5_5 AND regfil_5_6 AND N_PZ_1122);
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1145 <= ((NOT N_PZ_1117)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND N_PZ_2236));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1157 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND alures(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT N_PZ_1373 AND NOT _COND_18(3)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1209 <= ((reset)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (state(3) AND state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND state(4) AND NOT state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1213 <= (NOT alusel(1) AND NOT alusel(2) AND m1/_addsub0000(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((alusel(1) AND alusel(2) AND aluopra(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(0) AND alusel(2) AND aluoprb(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(0) AND NOT alusel(2) AND N_PZ_1926)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(2) AND N_PZ_1926 AND NOT N_PZ_2177)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND m1/Mmux__old_resi_28_I7_Result30 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1926 AND N_PZ_2177)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND alusel(2) AND NOT N_PZ_1041)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/Mmux__old_resi_28_I7_Result30 AND m1/_addsub0000(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(0) AND alusel(2) AND aluoprb(2) AND aluopra(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND NOT alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__old_resi_28_I7_Result30 AND N_PZ_1076 AND N_PZ_1043));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1214 <= (alusel(1) AND NOT alusel(2) AND m1/Msub__AUX_23__xor0019)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((alusel(1) AND alusel(2) AND aluopra(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(0) AND alusel(2) AND aluoprb(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND alusel(2) AND N_PZ_1092)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND NOT alusel(2) AND NOT m1/_addsub0000(6) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/_addsub0000(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND m1/Mmux__old_resi_28_I3_Result28 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/_addsub0000(6) AND m1/_addsub0000(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(0) AND alusel(2) AND aluoprb(7) AND aluopra(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND NOT alusel(2) AND NOT m1/_addsub0000(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/_addsub0000(6) AND m1/_addsub0000(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND NOT alusel(2) AND m1/_addsub0000(6) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/_addsub0000(5) AND m1/_addsub0000(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(2) AND m1/Msub__AUX_23__xor0019 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Msub__AUX_23__xor0016 AND NOT m1/Msub__AUX_23__xor0013 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Msub__AUX_23__xor0010 AND N_PZ_1999)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND NOT alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__old_resi_28_I3_Result28 AND m1/_addsub0000(4) AND m1/_addsub0000(6) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/_addsub0000(5) AND NOT m1/_addsub0000(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND m1/Mmux__old_resi_28_I3_Result28 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Msub__AUX_23__xor0019 AND NOT m1/Msub__AUX_23__xor0016 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Msub__AUX_23__xor0013 AND NOT m1/Msub__AUX_23__xor0010 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Msub__AUX_23__xor0007 AND NOT N_PZ_1926 AND N_PZ_2177));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1223 <= (N_PZ_2021 AND pc(10) AND pc(8) AND pc(9) AND pc(11));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1246 <= ((N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (state(4) AND state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (state(3) AND NOT state(1) AND state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT N_PZ_1066 AND NOT N_PZ_1065)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1066 AND NOT state(0) AND NOT N_PZ_1065));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1260 <= (NOT alusel(1) AND NOT alusel(2) AND m1/_addsub0000(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((alusel(1) AND alusel(2) AND aluopra(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(0) AND alusel(2) AND aluoprb(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(0) AND NOT alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/Msub__AUX_23__xor0007)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(2) AND m1/Msub__AUX_23__xor0007 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1926)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(2) AND m1/Msub__AUX_23__xor0007 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_2177)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND alusel(2) AND N_PZ_1082)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(0) AND alusel(2) AND aluoprb(3) AND aluopra(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND m1/Mmux__old_resi_28_I7_Result30 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Msub__AUX_23__xor0007 AND NOT N_PZ_1926 AND N_PZ_2177)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/Mmux__old_resi_28_I7_Result30 AND m1/_addsub0000(2) AND m1/_addsub0000(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND NOT alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__old_resi_28_I7_Result30 AND N_PZ_1076 AND N_PZ_1043 AND m1/_addsub0000(2)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1261 <= (alusel(1) AND NOT alusel(2) AND m1/Msub__AUX_23__xor0016)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((alusel(1) AND alusel(2) AND aluopra(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND m1/Mmux__old_resi_28_I3_Result28 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/_addsub0000(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(0) AND alusel(2) AND aluoprb(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND alusel(2) AND N_PZ_1059)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND NOT alusel(2) AND NOT m1/_addsub0000(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/_addsub0000(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND NOT alusel(2) AND m1/_addsub0000(6) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/_addsub0000(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(0) AND alusel(2) AND aluoprb(6) AND aluopra(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND m1/Mmux__old_resi_28_I3_Result28 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Msub__AUX_23__xor0016 AND NOT m1/Msub__AUX_23__xor0013 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Msub__AUX_23__xor0010)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/Mmux__old_resi_28_I3_Result28 AND m1/Msub__AUX_23__xor0016 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Msub__AUX_23__xor0013 AND NOT m1/Msub__AUX_23__xor0010)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND NOT alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__old_resi_28_I3_Result28 AND m1/_addsub0000(4) AND NOT m1/_addsub0000(6) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/_addsub0000(5)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1262 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND alures(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(1).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT N_PZ_1373 AND NOT _COND_18(1)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1265 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND alures(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(5).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT N_PZ_1373 AND NOT _COND_18(5)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1266 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND alures(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(7).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT _COND_18(7) AND NOT N_PZ_1373));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1268 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT alures(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(0).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND _COND_18(0) AND NOT N_PZ_1373));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1347 <= (regfil_4_2 AND regfil_4_1 AND regfil_4_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_4_3 AND regfil_4_6 AND regfil_4_5 AND regfil_4_4);
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1373 <= (regs(2) AND regs(1) AND NOT regs(0));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1432 <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT data(5).PIN);
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1527 <= ((NOT alusel(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1054 AND NOT aluoprb(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND alusel(0) AND NOT aluopra(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND NOT N_PZ_1054)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND NOT alusel(0) AND N_PZ_1054));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1528 <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819);
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1533 <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT data(5).PIN);
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1536 <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND data(5).PIN);
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1580 <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1916);
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1725 <= ((regfil_5_1 AND sp(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_0 AND regfil_5_1 AND sp(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_0 AND sp(0) AND sp(1)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1799 <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_1_0 AND regfil_1_2 AND regfil_1_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_0_1 AND regfil_1_3 AND regfil_1_6 AND regfil_1_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_0_3 AND regfil_1_5 AND regfil_1_7 AND regfil_0_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_0_0 AND regfil_0_4);
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1819 <= (NOT data(4).PIN AND data(5).PIN);
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1848 <= ((regfil_4_5 AND sp(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_4_5 AND NOT sp(13)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1849 <= ((regfil_4_7 AND sp(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_4_7 AND NOT sp(15)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1870 <= ((regfil_4_0 AND Madd__addsub0000__or0006)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_4_0 AND NOT Madd__addsub0000__or0006));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1887 <= (NOT regfil_7_5 AND NOT regfil_7_6);
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1888 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND alures(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT N_PZ_1373 AND NOT _COND_18(6)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1890 <= ((regfil_7_1 AND NOT regfil_7_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_7_1 AND regfil_7_2));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1891 <= (NOT state(0) AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND NOT N_PZ_2236);
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1894 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1905 <= regfil_4_6
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((NOT regfil_4_5 AND regfil_2_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_2_6 AND _addsub0001(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_4_5 AND NOT regfil_2_6 AND NOT _addsub0001(13)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1913 <= (regfil_4_1 AND NOT _addsub0000(9));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1916 <= (data(3).PIN AND NOT data(2).PIN AND N_PZ_1819);
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1921 <= ((N_PZ_1373)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND NOT regd(0)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1926 <= ((m1/Msub__sub0000__or0001 AND N_PZ_1041)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT m1/Msub__sub0000__or0001 AND NOT N_PZ_1041));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1929 <= ((regfil_4_4 AND sp(12))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_4_4 AND NOT sp(12)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1941 <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN);
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1943 <= ((N_PZ_1157)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(3).PIN));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1944 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND alures(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(2).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT N_PZ_1373 AND NOT _COND_18(2)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1945 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT alures(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(2).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT N_PZ_1373 AND _COND_18(2)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1946 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT alures(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(1).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT N_PZ_1373 AND _COND_18(1)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1948 <= ((NOT reset AND state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1954 <= ((NOT aluopra(1) AND NOT m1/Msub__sub0000__or0001 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT aluopra(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND alusel(0) AND NOT aluopra(1) AND NOT aluopra(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND NOT N_PZ_1076 AND NOT N_PZ_1043)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND NOT alusel(0) AND N_PZ_1076 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Madd__addsub0000__or0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND NOT alusel(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Madd__addsub0000__or0000 AND NOT aluopra(0)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1966 <= ((NOT data(0).PIN AND data(7).PIN AND N_PZ_1916 AND parity)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND NOT data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND data(7).PIN AND NOT data(5).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND NOT data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND NOT data(5).PIN AND NOT zero)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(3).PIN AND NOT data(2).PIN AND NOT data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND N_PZ_1819 AND NOT parity)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND data(7).PIN AND data(5).PIN AND sign)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND data(7).PIN AND NOT data(5).PIN AND carry)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND NOT data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND data(7).PIN AND data(5).PIN AND NOT sign)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND NOT data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND data(7).PIN AND NOT data(5).PIN AND NOT carry)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND data(7).PIN AND NOT data(5).PIN AND zero));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1981 <= ((regfil_5_5 AND sp(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_5 AND NOT sp(5)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1982 <= ((regfil_5_7 AND sp(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_7 AND NOT sp(7)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1986 <= ((NOT regfil_7_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_7_1 AND NOT regfil_7_2));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1995 <= (regfil_4_5 AND regfil_4_4 AND N_PZ_1143 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__AUX_10_Mxor_Result(12)__xor0000);
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1996 <= ((NOT reset AND state(2) AND NOT state(4) AND NOT state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1066 AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT N_PZ_1373));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1997 <= N_PZ_1141
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((N_PZ_1260 AND N_PZ_1214 AND NOT N_PZ_2124)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1260 AND NOT N_PZ_1214 AND N_PZ_2124)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1260 AND N_PZ_1214 AND N_PZ_2124)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1260 AND NOT N_PZ_1214 AND NOT N_PZ_2124));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_1999 <= (alusel(0) AND NOT m1/Msub__AUX_23__xor0007 AND NOT N_PZ_1926 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2177);
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2000 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT alures(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(5).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT N_PZ_1373 AND _COND_18(5)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2001 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT alures(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(7).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND _COND_18(7) AND NOT N_PZ_1373));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2004 <= ((NOT regfil_5_2 AND NOT regfil_1_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_2 AND NOT Madd__addsub0000__or0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_1_2 AND NOT Madd__addsub0000__or0000));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2021 <= (pc(7) AND pc(3) AND pc(6) AND pc(4) AND N_PZ_2033 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	pc(5));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2031 <= ((NOT regfil_2_5 AND Madd__AUX_9__or0011)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_2_5 AND NOT _addsub0001(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (Madd__AUX_9__or0011 AND NOT _addsub0001(13)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2033 <= (pc(0) AND pc(1) AND pc(2));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2046 <= (regfil_4_5 AND regfil_4_4 AND NOT Madd__AUX_10__or0010 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__AUX_10_Mxor_Result(12)__xor0000);
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2047 <= regfil_5_4
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((NOT regfil_5_3 AND NOT regfil_3_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_3 AND NOT N_PZ_2358)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_3_3 AND NOT N_PZ_2358));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2048 <= regfil_5_5
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((NOT regfil_5_4 AND N_PZ_2047)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_3_4 AND NOT N_PZ_2047));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2049 <= regfil_5_6
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((NOT regfil_5_5 AND N_PZ_2048)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_3_5 AND NOT N_PZ_2048));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2050 <= regfil_5_7
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((NOT regfil_3_6 AND NOT N_PZ_2049)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_6 AND N_PZ_2049));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2052 <= _addsub0001(11)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((NOT regfil_2_2 AND NOT _addsub0001(10))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_2_2 AND Madd__AUX_9__or0008)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT _addsub0001(10) AND Madd__AUX_9__or0008));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2054 <= _addsub0000(14)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((NOT regfil_0_5 AND Madd__AUX_8__or0011)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_0_5 AND NOT _addsub0000(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (Madd__AUX_8__or0011 AND NOT _addsub0000(13)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2055 <= _addsub0001(15)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((NOT regfil_2_6 AND NOT N_PZ_1905)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1905 AND N_PZ_2031));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2056 <= _addsub0000(15)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((NOT regfil_0_6 AND NOT N_PZ_2054)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2054 AND NOT _addsub0000(14)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2057 <= regfil_4_1
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((NOT regfil_4_0 AND NOT regfil_2_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_4_0 AND Madd__addsub0001__or0006)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_2_0 AND Madd__addsub0001__or0006));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2067 <= ((N_PZ_1209 AND NOT N_PZ_1145)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1209 AND N_PZ_1223 AND pc(12)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2105 <= ((regfil_4_6 AND NOT sp(14))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_4_6 AND sp(14)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2106 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT alures(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(6).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT N_PZ_1373 AND _COND_18(6)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2108 <= ((NOT sp(5) AND N_PZ_1981)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT sp(4) AND NOT N_PZ_2168 AND NOT N_PZ_1981)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2168 AND NOT N_PZ_1981 AND N_PZ_2111));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2111 <= ((NOT regfil_5_3 AND NOT sp(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_3 AND NOT Madd__AUX_11__or0001)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT sp(3) AND NOT Madd__AUX_11__or0001));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2114 <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819);
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2124 <= ((N_PZ_1213 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mxor__xor0001_Mxor__xor0000__xor0001)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1213 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/Mxor__xor0001_Mxor__xor0000__xor0001));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2147 <= ((NOT regfil_5_6 AND NOT regfil_1_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_6 AND Madd__addsub0000__or0004)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_1_6 AND Madd__addsub0000__or0004));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2148 <= ((NOT regfil_5_4 AND NOT regfil_1_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_4 AND Madd__addsub0000__or0002)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_1_4 AND Madd__addsub0000__or0002));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2155 <= ((NOT N_PZ_2114)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND NOT data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT data(5).PIN));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2168 <= ((regfil_5_4 AND NOT sp(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_4 AND sp(4)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2169 <= ((regfil_5_6 AND NOT sp(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_6 AND sp(6)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2177 <= (NOT N_PZ_1076 AND NOT N_PZ_1043 AND alucin);
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2180 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT alures(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(3).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT N_PZ_1373 AND _COND_18(3)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2181 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT alures(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(4).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT N_PZ_1373 AND _COND_18(4)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2186 <= ((NOT reset AND state(2) AND NOT state(4) AND NOT state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0) AND regd(2) AND regd(1) AND NOT regd(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND NOT regd(0) AND NOT N_PZ_1373));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2196 <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT N_PZ_1373 AND N_PZ_1129);
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2226 <= ((regfil_2_7 AND NOT N_PZ_2055)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2055 AND _addsub0001(15)));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2232 <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND data(6).PIN AND data(7).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND data(1).PIN AND data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2236 <= ((NOT data(2).PIN AND data(1).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(1).PIN AND NOT N_PZ_1916));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2358 <= ((regfil_3_2 AND regfil_5_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_3_2 AND Madd__addsub0001__or0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_2 AND Madd__addsub0001__or0000));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2362 <= ((regfil_4_0 AND sp(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_4_0 AND NOT sp(8) AND NOT Madd__AUX_11__or0006)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_4_0 AND sp(8) AND NOT Madd__AUX_11__or0006));
</td></tr><tr><td>
</td></tr><tr><td>
N_PZ_2405 <= (addrhold(7) AND addrhold(3) AND addrhold(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(9) AND addrhold(8) AND addrhold(1) AND addrhold(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(10) AND addrhold(4) AND addrhold(11) AND addrhold(5) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(6) AND N_PZ_1948);
</td></tr><tr><td>
</td></tr><tr><td>
_COND_18(0) <= ((N_PZ_1373 AND NOT regfil_6_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND regs(1) AND NOT regfil_7_0 AND regs(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND NOT regs(1) AND NOT regfil_5_0 AND regs(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND NOT regs(1) AND NOT regfil_4_0 AND NOT regs(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND regs(1) AND NOT regfil_3_0 AND regs(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND regs(1) AND NOT regs(0) AND NOT regfil_2_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_1_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_0_0));
</td></tr><tr><td>
</td></tr><tr><td>
_COND_18(1) <= ((N_PZ_1373 AND NOT regfil_6_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND regs(1) AND NOT regfil_7_1 AND regs(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND NOT regs(1) AND NOT regfil_4_1 AND NOT regs(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_5_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND regs(1) AND regs(0) AND NOT regfil_3_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND regs(1) AND NOT regs(0) AND NOT regfil_2_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_1_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_0_1));
</td></tr><tr><td>
</td></tr><tr><td>
_COND_18(2) <= ((N_PZ_1373 AND NOT regfil_6_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND regs(1) AND NOT regfil_7_2 AND regs(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND NOT regs(1) AND NOT regfil_4_2 AND NOT regs(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_5_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND regs(1) AND regs(0) AND NOT regfil_3_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND regs(1) AND NOT regs(0) AND NOT regfil_2_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_1_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_0_2));
</td></tr><tr><td>
</td></tr><tr><td>
_COND_18(3) <= ((N_PZ_1373 AND NOT regfil_6_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND regs(1) AND NOT regfil_7_3 AND regs(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND NOT regs(1) AND NOT regfil_5_3 AND regs(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_4_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND regs(1) AND regs(0) AND NOT regfil_3_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND regs(1) AND NOT regs(0) AND NOT regfil_2_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_1_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_0_3));
</td></tr><tr><td>
</td></tr><tr><td>
_COND_18(4) <= ((N_PZ_1373 AND NOT regfil_6_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND regs(1) AND regs(0) AND NOT regfil_7_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_5_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_4_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND regs(1) AND regs(0) AND NOT regfil_3_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND regs(1) AND NOT regs(0) AND NOT regfil_2_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_1_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_0_4));
</td></tr><tr><td>
</td></tr><tr><td>
_COND_18(5) <= ((N_PZ_1373 AND NOT regfil_6_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND regs(1) AND regs(0) AND NOT regfil_7_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_5_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_4_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND regs(1) AND regs(0) AND NOT regfil_3_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND regs(1) AND NOT regs(0) AND NOT regfil_2_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_1_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_0_5));
</td></tr><tr><td>
</td></tr><tr><td>
_COND_18(6) <= ((N_PZ_1373 AND NOT regfil_6_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND regs(1) AND regs(0) AND NOT regfil_7_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_5_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_4_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND regs(1) AND regs(0) AND NOT regfil_3_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND regs(1) AND NOT regs(0) AND NOT regfil_2_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_1_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_0_6));
</td></tr><tr><td>
</td></tr><tr><td>
_COND_18(7) <= ((N_PZ_1373 AND NOT regfil_6_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND regs(1) AND regs(0) AND NOT regfil_7_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND NOT regs(1) AND NOT regfil_5_7 AND regs(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_4_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND regs(1) AND regs(0) AND NOT regfil_3_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND regs(1) AND NOT regs(0) AND NOT regfil_2_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_1_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_0_7));
</td></tr><tr><td>
</td></tr><tr><td>
_addsub0000(9) <= regfil_4_1
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR (regfil_4_0 AND NOT Madd__addsub0000__or0006);
</td></tr><tr><td>
</td></tr><tr><td>
_addsub0000(11) <= regfil_4_3
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR (regfil_4_2 AND N_PZ_1913);
</td></tr><tr><td>
</td></tr><tr><td>
_addsub0000(12) <= regfil_4_4
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR (regfil_4_3 AND NOT _addsub0000(11));
</td></tr><tr><td>
</td></tr><tr><td>
_addsub0000(13) <= regfil_4_5
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR (regfil_4_4 AND NOT _addsub0000(12));
</td></tr><tr><td>
</td></tr><tr><td>
_addsub0000(14) <= regfil_4_6
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR (regfil_4_5 AND NOT _addsub0000(13));
</td></tr><tr><td>
</td></tr><tr><td>
_addsub0000(15) <= regfil_4_7
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR (regfil_4_6 AND NOT _addsub0000(14));
</td></tr><tr><td>
</td></tr><tr><td>
_addsub0001(10) <= regfil_4_2
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR (regfil_4_1 AND regfil_4_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__addsub0001__or0006);
</td></tr><tr><td>
</td></tr><tr><td>
_addsub0001(11) <= regfil_4_3
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR (regfil_4_2 AND NOT _addsub0001(10));
</td></tr><tr><td>
</td></tr><tr><td>
_addsub0001(12) <= regfil_4_4
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR (regfil_4_3 AND NOT _addsub0001(11));
</td></tr><tr><td>
</td></tr><tr><td>
_addsub0001(13) <= regfil_4_5
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR (regfil_4_4 AND NOT _addsub0001(12));
</td></tr><tr><td>
</td></tr><tr><td>
_addsub0001(15) <= regfil_4_7
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR (regfil_4_6 AND regfil_4_5 AND NOT _addsub0001(13));
</td></tr><tr><td>
</td></tr><tr><td>
_cmp_eq0004 <= (data(4).PIN AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN);
</td></tr><tr><td>
</td></tr><tr><td>
_mux000762 <= ((NOT state(3) AND NOT data(4).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND NOT N_PZ_1819 AND NOT N_PZ_2236 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_7_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT data(3).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND NOT N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_2236)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT data(3).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND NOT N_PZ_1819 AND NOT N_PZ_2236 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_7_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT data(3).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND NOT N_PZ_2236 AND regfil_7_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1887)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND NOT N_PZ_2236 AND regfil_4_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND NOT N_PZ_2236 AND regfil_4_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_2046)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND data(5).PIN AND NOT carry AND NOT N_PZ_1819 AND NOT N_PZ_2236)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_2236 AND carryhold)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND NOT N_PZ_2236 AND NOT regfil_4_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_4_6 AND N_PZ_2046)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT data(5).PIN AND NOT regfil_4_7 AND N_PZ_2226)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT data(5).PIN AND Madd__addsub0001__or0006 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2226)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT data(5).PIN AND NOT N_PZ_1347 AND N_PZ_2226)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND N_PZ_2236 AND N_PZ_1849 AND sp(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_2236 AND NOT regfil_4_7 AND regfil_0_7 AND NOT N_PZ_2056)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_2236 AND NOT regfil_4_7 AND N_PZ_2056 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	_addsub0000(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_2236 AND regfil_0_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__addsub0000__or0006 AND NOT N_PZ_2056)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_2236 AND Madd__addsub0000__or0006 AND N_PZ_2056 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	_addsub0000(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND regfil_4_7 AND regfil_0_7 AND NOT N_PZ_2056 AND NOT N_PZ_1347)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND regfil_4_7 AND N_PZ_2056 AND _addsub0000(15) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1347)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND N_PZ_2236 AND NOT Madd__AUX_11__or0012 AND N_PZ_2105 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1849)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND N_PZ_2236 AND NOT N_PZ_2105 AND sp(14) AND NOT N_PZ_1849)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT data(5).PIN AND regfil_4_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__addsub0001__or0006 AND N_PZ_1347 AND NOT N_PZ_2226)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_2236 AND regfil_4_7 AND NOT regfil_0_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__addsub0000__or0006 AND NOT N_PZ_2056 AND N_PZ_1347)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_2236 AND regfil_4_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__addsub0000__or0006 AND N_PZ_2056 AND NOT _addsub0000(15) AND N_PZ_1347));
</td></tr><tr><td>
</td></tr><tr><td>
_mux0009(2)72 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1916 AND regfil_5_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND NOT regfil_5_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_5_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND NOT regfil_5_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_5_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_5_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_5_1 AND NOT regfil_5_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND regfil_5_2 AND sp(2) AND N_PZ_1725)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND regfil_5_2 AND NOT sp(2) AND NOT N_PZ_1725)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND NOT regfil_5_2 AND sp(2) AND NOT N_PZ_1725)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND NOT regfil_5_2 AND NOT sp(2) AND N_PZ_1725)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_3_2 AND regfil_5_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__addsub0001__or0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_3_2 AND NOT regfil_5_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__addsub0001__or0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_3_2 AND regfil_5_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__addsub0001__or0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_3_2 AND NOT regfil_5_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__addsub0001__or0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_5_2 AND regfil_1_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__addsub0000__or0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_5_2 AND NOT regfil_1_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__addsub0000__or0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_5_2 AND regfil_1_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__addsub0000__or0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_5_2 AND NOT regfil_1_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__addsub0000__or0000));
</td></tr><tr><td>
</td></tr><tr><td>
_mux0009(4)72 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT N_PZ_2236 AND regfil_5_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1819 AND N_PZ_2236 AND regfil_5_4 AND NOT N_PZ_1122)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_3_4 AND N_PZ_2047)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_3_4 AND NOT N_PZ_2047)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2236 AND N_PZ_2168 AND N_PZ_2111)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2236 AND NOT N_PZ_2168 AND NOT N_PZ_2111)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2236 AND regfil_5_4 AND regfil_1_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__addsub0000__or0002)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2236 AND regfil_5_4 AND NOT regfil_1_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__addsub0000__or0002)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2236 AND NOT regfil_5_4 AND regfil_1_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__addsub0000__or0002)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2236 AND NOT regfil_5_4 AND NOT regfil_1_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__addsub0000__or0002)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1819 AND N_PZ_2236 AND regfil_5_3 AND regfil_5_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_5_1 AND regfil_5_2 AND NOT N_PZ_1122));
</td></tr><tr><td>
</td></tr><tr><td>
_mux0009(5)72 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT N_PZ_2236 AND regfil_5_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1819 AND N_PZ_2236 AND regfil_5_5 AND NOT N_PZ_1122)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1819 AND N_PZ_2236 AND NOT regfil_5_5 AND N_PZ_1122)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_3_5 AND N_PZ_2048)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_3_5 AND NOT N_PZ_2048)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND sp(4) AND NOT N_PZ_2168 AND N_PZ_1981)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND NOT sp(4) AND NOT N_PZ_2168 AND NOT N_PZ_1981)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND N_PZ_2168 AND N_PZ_1981 AND NOT N_PZ_2111)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND N_PZ_2168 AND NOT N_PZ_1981 AND N_PZ_2111)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_5_5 AND regfil_1_5 AND NOT N_PZ_2148)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_5_5 AND NOT regfil_1_5 AND N_PZ_2148)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_5_5 AND regfil_1_5 AND N_PZ_2148)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_5_5 AND NOT regfil_1_5 AND NOT N_PZ_2148));
</td></tr><tr><td>
</td></tr><tr><td>
_mux0009(6)72 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT N_PZ_2236 AND regfil_5_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1819 AND N_PZ_2236 AND regfil_5_6 AND NOT N_PZ_1143)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1819 AND N_PZ_2236 AND regfil_5_5 AND NOT N_PZ_1143 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1122)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_3_6 AND N_PZ_2049)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_3_6 AND NOT N_PZ_2049)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2236 AND N_PZ_2108 AND N_PZ_2169)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2236 AND NOT N_PZ_2108 AND NOT N_PZ_2169)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2236 AND regfil_5_6 AND regfil_1_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__addsub0000__or0004)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2236 AND regfil_5_6 AND NOT regfil_1_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__addsub0000__or0004)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2236 AND NOT regfil_5_6 AND regfil_1_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__addsub0000__or0004)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2236 AND NOT regfil_5_6 AND NOT regfil_1_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__addsub0000__or0004));
</td></tr><tr><td>
</td></tr><tr><td>
_mux0009(7)72 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT N_PZ_2236 AND regfil_5_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1819 AND regfil_5_7 AND N_PZ_2236 AND NOT N_PZ_1143)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1819 AND NOT regfil_5_7 AND N_PZ_2236 AND N_PZ_1143)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_3_7 AND N_PZ_2050)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_3_7 AND NOT N_PZ_2050)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND N_PZ_2108 AND N_PZ_2169 AND NOT N_PZ_1982)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND NOT N_PZ_2108 AND N_PZ_2169 AND N_PZ_1982)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND NOT N_PZ_2169 AND sp(6) AND N_PZ_1982)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND NOT N_PZ_2169 AND NOT sp(6) AND NOT N_PZ_1982)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_5_7 AND regfil_1_7 AND NOT N_PZ_2147)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_5_7 AND NOT regfil_1_7 AND N_PZ_2147)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_5_7 AND regfil_1_7 AND N_PZ_2147)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_5_7 AND NOT regfil_1_7 AND NOT N_PZ_2147));
</td></tr><tr><td>
</td></tr><tr><td>
_mux0010(8)71 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND regfil_5_7 AND NOT N_PZ_2236)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1819 AND NOT regfil_5_7 AND N_PZ_2236 AND regfil_4_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1819 AND N_PZ_2236 AND regfil_4_0 AND NOT N_PZ_1143)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1819 AND regfil_5_7 AND N_PZ_2236 AND NOT regfil_4_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1143)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2236 AND regfil_0_0 AND NOT N_PZ_1870)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2236 AND NOT regfil_0_0 AND N_PZ_1870)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_4_0 AND regfil_2_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__addsub0001__or0006)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_4_0 AND NOT regfil_2_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__addsub0001__or0006)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_4_0 AND regfil_2_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__addsub0001__or0006)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_4_0 AND NOT regfil_2_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__addsub0001__or0006)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2236 AND regfil_4_0 AND sp(8) AND NOT Madd__AUX_11__or0006)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2236 AND regfil_4_0 AND NOT sp(8) AND Madd__AUX_11__or0006)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2236 AND NOT regfil_4_0 AND sp(8) AND Madd__AUX_11__or0006)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2236 AND NOT regfil_4_0 AND NOT sp(8) AND NOT Madd__AUX_11__or0006));
</td></tr><tr><td>
</td></tr><tr><td>
_mux0010(9)71 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1916 AND regfil_4_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND NOT regfil_5_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_4_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1143)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_2_1 AND N_PZ_2057)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_2_1 AND NOT N_PZ_2057)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND regfil_0_1 AND NOT Madd__AUX_8__or0008)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND _addsub0000(9) AND NOT Madd__AUX_8__or0008)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND regfil_4_1 AND Madd__AUX_11__or0008)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND sp(9) AND Madd__AUX_11__or0008)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND Madd__AUX_11__or0008 AND N_PZ_2362)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_5_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_1 AND regfil_4_0 AND N_PZ_1143)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND regfil_0_0 AND NOT Madd__AUX_8__or0008 AND N_PZ_1870)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND regfil_4_1 AND sp(9) AND N_PZ_2362)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND regfil_0_1 AND regfil_0_0 AND _addsub0000(9) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1870));
</td></tr><tr><td>
</td></tr><tr><td>
_mux0010(10)71 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1916 AND regfil_4_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND NOT regfil_5_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_4_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1143)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND regfil_4_2 AND Madd__AUX_11__or0009)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND sp(10) AND Madd__AUX_11__or0009)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND Madd__AUX_11__or0009 AND NOT Madd__AUX_11__or0008)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_0_2 AND Madd__AUX_8__or0009)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND Madd__AUX_8__or0009 AND Madd__AUX_8__or0008)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_2 AND N_PZ_1913 AND Madd__AUX_8__or0009)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND regfil_4_2 AND sp(10) AND NOT Madd__AUX_11__or0008)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_2_2 AND _addsub0001(10) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__AUX_9__or0008)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_2_2 AND NOT _addsub0001(10) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__AUX_9__or0008)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_2_2 AND _addsub0001(10) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__AUX_9__or0008)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_2_2 AND NOT _addsub0001(10) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__AUX_9__or0008)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_4_2 AND NOT N_PZ_1913 AND Madd__AUX_8__or0009)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_2 AND regfil_0_2 AND N_PZ_1913 AND Madd__AUX_8__or0008)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_5_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_2 AND regfil_4_1 AND regfil_4_0 AND N_PZ_1143)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_4_2 AND regfil_0_2 AND NOT N_PZ_1913 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__AUX_8__or0008));
</td></tr><tr><td>
</td></tr><tr><td>
_mux0010(11)71 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1916 AND regfil_4_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_3 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1143)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_3 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__AUX_10_Mxor_Result(12)__xor0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_2_3 AND N_PZ_2052)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_2_3 AND NOT N_PZ_2052)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND regfil_0_3 AND _addsub0000(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__AUX_8__or0009)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND regfil_0_3 AND NOT _addsub0000(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__AUX_8__or0009)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND NOT regfil_0_3 AND _addsub0000(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__AUX_8__or0009)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND NOT regfil_0_3 AND NOT _addsub0000(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__AUX_8__or0009)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND regfil_4_3 AND sp(11) AND NOT Madd__AUX_11__or0009)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND regfil_4_3 AND NOT sp(11) AND Madd__AUX_11__or0009)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND NOT regfil_4_3 AND sp(11) AND Madd__AUX_11__or0009)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND NOT regfil_4_3 AND NOT sp(11) AND NOT Madd__AUX_11__or0009)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_5_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_4_2 AND regfil_4_1 AND regfil_4_0 AND NOT regfil_4_3 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1143));
</td></tr><tr><td>
</td></tr><tr><td>
_mux0010(12)71 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1916 AND Madd__AUX_10__or0010 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__AUX_10_Mxor_Result(12)__xor0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1916 AND NOT Madd__AUX_10__or0010 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__AUX_10_Mxor_Result(12)__xor0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1143)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__AUX_10_Mxor_Result(12)__xor0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND NOT regfil_4_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1143 AND Madd__AUX_10_Mxor_Result(12)__xor0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_2_4 AND Madd__AUX_9__or0011)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND _addsub0001(12) AND Madd__AUX_9__or0011)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1819 AND regfil_0_4 AND Madd__AUX_8__or0011)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1819 AND _addsub0000(12) AND Madd__AUX_8__or0011)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1819 AND NOT Madd__AUX_8__or0010 AND Madd__AUX_8__or0011)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1819 AND Madd__AUX_11__or0010 AND NOT N_PZ_1929)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1819 AND NOT Madd__AUX_11__or0010 AND N_PZ_1929)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_2_3 AND NOT N_PZ_2052 AND Madd__AUX_9__or0011)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND _addsub0001(11) AND N_PZ_2052 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__AUX_9__or0011)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1819 AND regfil_0_4 AND _addsub0000(12) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__AUX_8__or0010)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_2_3 AND regfil_2_4 AND _addsub0001(12) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_2052)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_2_4 AND _addsub0001(11) AND _addsub0001(12) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2052));
</td></tr><tr><td>
</td></tr><tr><td>
_mux0010(13)71 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1916 AND regfil_4_4 AND Madd__AUX_10__or0010)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1916 AND regfil_4_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT Madd__AUX_10_Mxor_Result(12)__xor0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_5 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1995)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1916 AND NOT regfil_4_4 AND NOT Madd__AUX_10__or0010 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__AUX_10_Mxor_Result(12)__xor0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND NOT regfil_4_5 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_4_4 AND N_PZ_1143 AND Madd__AUX_10_Mxor_Result(12)__xor0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_2_5 AND Madd__AUX_9__or0011 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _addsub0001(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_2_5 AND NOT Madd__AUX_9__or0011 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	_addsub0001(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_2_5 AND Madd__AUX_9__or0011 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	_addsub0001(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_2_5 AND NOT Madd__AUX_9__or0011 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _addsub0001(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND regfil_0_5 AND Madd__AUX_8__or0011 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _addsub0000(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND regfil_0_5 AND NOT Madd__AUX_8__or0011 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	_addsub0000(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND NOT regfil_0_5 AND Madd__AUX_8__or0011 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	_addsub0000(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND NOT regfil_0_5 AND NOT Madd__AUX_8__or0011 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _addsub0000(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND Madd__AUX_11__or0010 AND NOT N_PZ_1929 AND NOT N_PZ_1848)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND NOT Madd__AUX_11__or0010 AND NOT N_PZ_1929 AND N_PZ_1848)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND N_PZ_1929 AND sp(12) AND N_PZ_1848)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND N_PZ_1929 AND NOT sp(12) AND NOT N_PZ_1848));
</td></tr><tr><td>
</td></tr><tr><td>
_mux0010(14)71 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1916 AND regfil_4_5 AND NOT N_PZ_2046)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1995)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND NOT regfil_4_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1995)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1916 AND regfil_4_4 AND NOT Madd__AUX_10__or0010 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__AUX_10_Mxor_Result(12)__xor0000 AND NOT N_PZ_2046)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND N_PZ_1905 AND N_PZ_2031)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND regfil_0_6 AND N_PZ_2054)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND NOT regfil_0_6 AND NOT N_PZ_2054)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND Madd__AUX_11__or0012 AND N_PZ_2105)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1916 AND NOT Madd__AUX_11__or0012 AND NOT N_PZ_2105)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_2_5 AND NOT Madd__AUX_9__or0011 AND NOT N_PZ_1905)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_4_6 AND regfil_2_6 AND _addsub0001(13) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_2031)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_4_6 AND NOT regfil_2_6 AND _addsub0001(13) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_2031));
</td></tr><tr><td>
</td></tr><tr><td>
_mux0010(15)71 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1916 AND regfil_4_6 AND NOT N_PZ_2046)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND N_PZ_1916 AND NOT regfil_4_6 AND N_PZ_2046)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1995)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND NOT regfil_4_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_4_6 AND N_PZ_1995)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_2_7 AND N_PZ_2055)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_2_7 AND NOT N_PZ_2055)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_0_7 AND N_PZ_2056)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_0_7 AND NOT N_PZ_2056)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND Madd__AUX_11__or0012 AND N_PZ_2105 AND NOT N_PZ_1849)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND NOT Madd__AUX_11__or0012 AND N_PZ_2105 AND N_PZ_1849)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND NOT N_PZ_2105 AND sp(14) AND N_PZ_1849)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND NOT N_PZ_2105 AND NOT sp(14) AND NOT N_PZ_1849));
</td></tr><tr><td>
</td></tr><tr><td>
_mux0014(13)8 <= regfil_2_5
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((NOT data(4).PIN AND regfil_2_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(2).PIN AND regfil_2_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(1).PIN AND regfil_2_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(0).PIN AND regfil_2_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(6).PIN AND regfil_2_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(7).PIN AND regfil_2_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(5).PIN AND regfil_2_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(4).PIN AND NOT data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_0 AND regfil_2_0 AND regfil_3_1 AND regfil_2_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_2 AND regfil_2_2 AND regfil_3_3 AND regfil_3_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_5 AND regfil_2_3 AND regfil_3_6 AND regfil_2_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_7));
</td></tr><tr><td>
</td></tr><tr><td>
_mux003739 <= ((NOT state(3) AND state(2) AND NOT state(4) AND NOT state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0) AND NOT regd(2) AND addrhold(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND state(2) AND NOT state(4) AND NOT state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0) AND NOT regd(1) AND addrhold(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND state(2) AND NOT state(4) AND NOT state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0) AND regd(0) AND addrhold(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND data(7).PIN AND addrhold(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT data(1).PIN AND NOT data(6).PIN AND addrhold(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND data(0).PIN AND NOT data(6).PIN AND addrhold(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND data(6).PIN AND _cmp_eq0004 AND addrhold(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND data(6).PIN AND NOT N_PZ_1921 AND addrhold(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND state(2) AND NOT state(4) AND NOT state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND addrhold2(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT data(2).PIN AND NOT data(6).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND pc(15)));
</td></tr><tr><td>
</td></tr><tr><td>
_xor0000 <= (NOT regfil_5_7 AND NOT regfil_5_3 AND NOT regfil_5_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_5_1 AND NOT regfil_5_2 AND NOT regfil_5_4 AND NOT regfil_5_5 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_5_6);
</td></tr><tr><td>
</td></tr><tr><td>
_xor0068 <= (NOT regfil_1_0 AND NOT regfil_1_2 AND NOT regfil_1_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_1_3 AND NOT regfil_1_6 AND NOT regfil_1_4 AND NOT regfil_1_5 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_1_7);
</td></tr><tr><td>
FDCPE_addrhold20: FDCPE port map (addrhold2(0),regfil_5_0,clock,'0','0',addrhold2_CE(0));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold2_CE(0) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND data(5).PIN);
</td></tr><tr><td>
FDCPE_addrhold21: FDCPE port map (addrhold2(1),regfil_5_1,clock,'0','0',addrhold2_CE(1));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold2_CE(1) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND data(5).PIN);
</td></tr><tr><td>
FDCPE_addrhold22: FDCPE port map (addrhold2(2),regfil_5_2,clock,'0','0',addrhold2_CE(2));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold2_CE(2) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND data(5).PIN);
</td></tr><tr><td>
FDCPE_addrhold23: FDCPE port map (addrhold2(3),regfil_5_3,clock,'0','0',addrhold2_CE(3));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold2_CE(3) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND data(5).PIN);
</td></tr><tr><td>
FDCPE_addrhold24: FDCPE port map (addrhold2(4),regfil_5_4,clock,'0','0',addrhold2_CE(4));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold2_CE(4) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND data(5).PIN);
</td></tr><tr><td>
FDCPE_addrhold25: FDCPE port map (addrhold2(5),regfil_5_5,clock,'0','0',addrhold2_CE(5));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold2_CE(5) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND data(5).PIN);
</td></tr><tr><td>
FDCPE_addrhold26: FDCPE port map (addrhold2(6),regfil_5_6,clock,'0','0',addrhold2_CE(6));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold2_CE(6) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND data(5).PIN);
</td></tr><tr><td>
FDCPE_addrhold27: FDCPE port map (addrhold2(7),regfil_5_7,clock,'0','0',addrhold2_CE(7));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold2_CE(7) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND data(5).PIN);
</td></tr><tr><td>
FDCPE_addrhold28: FDCPE port map (addrhold2(8),regfil_4_0,clock,'0','0',addrhold2_CE(8));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold2_CE(8) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND data(5).PIN);
</td></tr><tr><td>
FDCPE_addrhold29: FDCPE port map (addrhold2(9),regfil_4_1,clock,'0','0',addrhold2_CE(9));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold2_CE(9) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND data(5).PIN);
</td></tr><tr><td>
FDCPE_addrhold210: FDCPE port map (addrhold2(10),regfil_4_2,clock,'0','0',addrhold2_CE(10));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold2_CE(10) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND data(5).PIN);
</td></tr><tr><td>
FDCPE_addrhold211: FDCPE port map (addrhold2(11),regfil_4_3,clock,'0','0',addrhold2_CE(11));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold2_CE(11) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND data(5).PIN);
</td></tr><tr><td>
FDCPE_addrhold212: FDCPE port map (addrhold2(12),regfil_4_4,clock,'0','0',addrhold2_CE(12));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold2_CE(12) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND data(5).PIN);
</td></tr><tr><td>
FDCPE_addrhold213: FDCPE port map (addrhold2(13),regfil_4_5,clock,'0','0',addrhold2_CE(13));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold2_CE(13) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND data(5).PIN);
</td></tr><tr><td>
FDCPE_addrhold214: FDCPE port map (addrhold2(14),regfil_4_6,clock,'0','0',addrhold2_CE(14));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold2_CE(14) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND data(5).PIN);
</td></tr><tr><td>
FDCPE_addrhold215: FDCPE port map (addrhold2(15),regfil_4_7,clock,'0','0',addrhold2_CE(15));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold2_CE(15) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND data(5).PIN);
</td></tr><tr><td>
FTCPE_addrhold0: FTCPE port map (addrhold(0),addrhold_T(0),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold_T(0) <= ((N_PZ_1948)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND data(0).PIN AND NOT addrhold(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT data(0).PIN AND addrhold(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(0) AND NOT addrhold2(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT addrhold(0) AND addrhold2(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND addrhold(0) AND N_PZ_1921 AND _xor0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT addrhold(0) AND N_PZ_1921 AND NOT _xor0000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(0) AND NOT pc(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(0) AND pc(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT addrhold(0) AND regfil_2_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT addrhold(0) AND regfil_2_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT addrhold(0) AND regfil_2_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT addrhold(0) AND regfil_2_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT addrhold(0) AND regfil_2_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT addrhold(0) AND regfil_2_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT addrhold(0) AND regfil_2_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT addrhold(0) AND regfil_2_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND addrhold(0) AND _xor0068)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT addrhold(0) AND NOT _xor0068)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND addrhold(0) AND NOT regfil_2_0 AND NOT regfil_2_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_2_2 AND NOT regfil_2_5 AND NOT regfil_2_3 AND NOT regfil_2_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_2_6 AND NOT regfil_2_4));
</td></tr><tr><td>
FTCPE_addrhold1: FTCPE port map (addrhold(1),addrhold_T(1),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold_T(1) <= ((addrhold(0) AND N_PZ_1948)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (addrhold(1) AND N_PZ_1133)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND data(1).PIN AND NOT addrhold(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT data(1).PIN AND addrhold(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(1) AND NOT addrhold2(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT addrhold(1) AND addrhold2(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(1) AND NOT pc(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(1) AND pc(1)));
</td></tr><tr><td>
FTCPE_addrhold2: FTCPE port map (addrhold(2),addrhold_T(2),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold_T(2) <= ((addrhold(2) AND N_PZ_1133)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (addrhold(0) AND addrhold(1) AND N_PZ_1948)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND data(2).PIN AND NOT addrhold(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT data(2).PIN AND addrhold(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(2) AND NOT addrhold2(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT addrhold(2) AND addrhold2(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(2) AND NOT pc(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(2) AND pc(2)));
</td></tr><tr><td>
FTCPE_addrhold3: FTCPE port map (addrhold(3),addrhold_T(3),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold_T(3) <= ((addrhold(3) AND N_PZ_1133)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (addrhold(0) AND addrhold(1) AND addrhold(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1948)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND data(3).PIN AND NOT addrhold(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT data(3).PIN AND addrhold(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(3) AND NOT addrhold2(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT addrhold(3) AND addrhold2(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND pc(3) AND NOT addrhold(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT pc(3) AND addrhold(3)));
</td></tr><tr><td>
FTCPE_addrhold4: FTCPE port map (addrhold(4),addrhold_T(4),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold_T(4) <= ((addrhold(4) AND N_PZ_1133)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (addrhold(3) AND addrhold(0) AND addrhold(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(2) AND N_PZ_1948)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND data(4).PIN AND NOT addrhold(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT data(4).PIN AND addrhold(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(4) AND NOT addrhold2(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT addrhold(4) AND addrhold2(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(4) AND NOT pc(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(4) AND pc(4)));
</td></tr><tr><td>
FTCPE_addrhold5: FTCPE port map (addrhold(5),addrhold_T(5),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold_T(5) <= ((addrhold(5) AND N_PZ_1133)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (addrhold(3) AND addrhold(0) AND addrhold(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(2) AND addrhold(4) AND N_PZ_1948)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND data(5).PIN AND NOT addrhold(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT data(5).PIN AND addrhold(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(5) AND NOT addrhold2(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT addrhold(5) AND addrhold2(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(5) AND NOT pc(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(5) AND pc(5)));
</td></tr><tr><td>
FTCPE_addrhold6: FTCPE port map (addrhold(6),addrhold_T(6),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold_T(6) <= ((addrhold(6) AND N_PZ_1133)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (addrhold(3) AND addrhold(0) AND addrhold(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(2) AND addrhold(4) AND addrhold(5) AND N_PZ_1948)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND data(6).PIN AND NOT addrhold(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT data(6).PIN AND addrhold(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(6) AND NOT addrhold2(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT addrhold(6) AND addrhold2(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(6) AND NOT pc(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(6) AND pc(6)));
</td></tr><tr><td>
FTCPE_addrhold7: FTCPE port map (addrhold(7),addrhold_T(7),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold_T(7) <= ((addrhold(7) AND N_PZ_1133)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND data(7).PIN AND NOT addrhold(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT data(7).PIN AND addrhold(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(0).PIN AND NOT addrhold(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(0).PIN AND addrhold(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (addrhold(3) AND addrhold(0) AND addrhold(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(2) AND addrhold(4) AND addrhold(5) AND addrhold(6) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1948)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(7) AND NOT addrhold2(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT addrhold(7) AND addrhold2(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(7) AND NOT pc(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(7) AND pc(7)));
</td></tr><tr><td>
FTCPE_addrhold8: FTCPE port map (addrhold(8),addrhold_T(8),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold_T(8) <= ((addrhold(8) AND N_PZ_1133)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(1).PIN AND NOT addrhold(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(1).PIN AND addrhold(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (addrhold(7) AND addrhold(3) AND addrhold(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(1) AND addrhold(2) AND addrhold(4) AND addrhold(5) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(6) AND N_PZ_1948)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(8) AND NOT addrhold2(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT addrhold(8) AND addrhold2(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(8) AND NOT pc(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(8) AND pc(8)));
</td></tr><tr><td>
FTCPE_addrhold9: FTCPE port map (addrhold(9),addrhold_T(9),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold_T(9) <= ((addrhold(9) AND N_PZ_1133)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(2).PIN AND NOT addrhold(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(2).PIN AND addrhold(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (addrhold(7) AND addrhold(3) AND addrhold(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(8) AND addrhold(1) AND addrhold(2) AND addrhold(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(5) AND addrhold(6) AND N_PZ_1948)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(9) AND NOT addrhold2(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT addrhold(9) AND addrhold2(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(9) AND NOT pc(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(9) AND pc(9)));
</td></tr><tr><td>
FTCPE_addrhold10: FTCPE port map (addrhold(10),addrhold_T(10),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold_T(10) <= ((addrhold(10) AND N_PZ_1133)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(3).PIN AND NOT addrhold(10))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(3).PIN AND addrhold(10))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(10) AND NOT addrhold2(10))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT addrhold(10) AND addrhold2(10))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (addrhold(7) AND addrhold(3) AND addrhold(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(9) AND addrhold(8) AND addrhold(1) AND addrhold(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(4) AND addrhold(5) AND addrhold(6) AND N_PZ_1948)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(10) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT pc(10))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(10) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	pc(10)));
</td></tr><tr><td>
FTCPE_addrhold11: FTCPE port map (addrhold(11),addrhold_T(11),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold_T(11) <= ((addrhold(11) AND N_PZ_1133)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(4).PIN AND NOT addrhold(11))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(4).PIN AND addrhold(11))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(11) AND NOT addrhold2(11))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT addrhold(11) AND addrhold2(11))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (addrhold(7) AND addrhold(3) AND addrhold(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(9) AND addrhold(8) AND addrhold(1) AND addrhold(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(10) AND addrhold(4) AND addrhold(5) AND addrhold(6) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1948)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT pc(11))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	pc(11)));
</td></tr><tr><td>
FTCPE_addrhold12: FTCPE port map (addrhold(12),addrhold_T(12),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold_T(12) <= ((N_PZ_2405)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (addrhold(12) AND N_PZ_1133)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(5).PIN AND NOT addrhold(12))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(5).PIN AND addrhold(12))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(12) AND NOT addrhold2(12))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT addrhold(12) AND addrhold2(12))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(12) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT pc(12))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(12) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	pc(12)));
</td></tr><tr><td>
FTCPE_addrhold13: FTCPE port map (addrhold(13),addrhold_T(13),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold_T(13) <= ((addrhold(13) AND N_PZ_1133)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (addrhold(12) AND N_PZ_2405)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(6).PIN AND NOT addrhold(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(6).PIN AND addrhold(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(13) AND NOT addrhold2(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT addrhold(13) AND addrhold2(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(13) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT pc(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(13) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	pc(13)));
</td></tr><tr><td>
FTCPE_addrhold14: FTCPE port map (addrhold(14),addrhold_T(14),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold_T(14) <= ((addrhold(14) AND N_PZ_1133)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (addrhold(13) AND addrhold(12) AND N_PZ_2405)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(7).PIN AND NOT addrhold(14))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(7).PIN AND addrhold(14))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(14) AND NOT addrhold2(14))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT addrhold(14) AND addrhold2(14))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(14) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT pc(14))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(14) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	pc(14)));
</td></tr><tr><td>
FTCPE_addrhold15: FTCPE port map (addrhold(15),addrhold_T(15),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addrhold_T(15) <= ((NOT reset AND NOT addrhold(15) AND _mux003739)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(2) AND N_PZ_1209 AND addrhold(15) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _mux003739)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND state(2) AND NOT state(4) AND NOT state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0) AND NOT N_PZ_1209 AND addrhold(15) AND NOT _mux003739)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(2) AND state(1) AND N_PZ_1066 AND addrhold(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(3) AND addrhold(0) AND addrhold(9) AND addrhold(8) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(1) AND addrhold(2) AND addrhold(10) AND addrhold(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(14) AND addrhold(13) AND addrhold(12) AND addrhold(11) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(5) AND addrhold(6) AND NOT _mux003739)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND state(2) AND state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1066 AND NOT N_PZ_1209 AND addrhold(7) AND addrhold(3) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(0) AND addrhold(9) AND addrhold(8) AND addrhold(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(2) AND addrhold(10) AND addrhold(4) AND addrhold(14) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(13) AND addrhold(12) AND addrhold(11) AND addrhold(5) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	addrhold(6) AND NOT _mux003739));
</td></tr><tr><td>
FDCPE_alucin: FDCPE port map (alucin,carry,clock,'0','0',alucin_CE);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;alucin_CE <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN);
</td></tr><tr><td>
FDCPE_alucout: FDCPE port map (alucout,alucout_D,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;alucout_D <= NOT ((NOT m1/Mmux__mux0000_Result1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__mux0000_Result3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((NOT m1/Mmux__mux0000_Result1 AND alusel(1) AND NOT alusel(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT alusel(2) AND m1/Msub__AUX_23__xor0019 AND NOT N_PZ_1092 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__mux0000_Result3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT m1/Mmux__mux0000_Result1 AND alusel(1) AND NOT alusel(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT alusel(2) AND N_PZ_1092 AND NOT aluopra(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__mux0000_Result3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT m1/Mmux__mux0000_Result1 AND NOT alusel(1) AND NOT alusel(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT alusel(2) AND N_PZ_1092 AND NOT m1/_addsub0000(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__mux0000_Result3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT m1/Mmux__mux0000_Result1 AND NOT alusel(1) AND NOT alusel(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT alusel(2) AND NOT N_PZ_1092 AND aluopra(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__mux0000_Result3)));
</td></tr><tr><td>
FDCPE_aluopra0: FDCPE port map (aluopra(0),aluopra_D(0),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;aluopra_D(0) <= NOT (((NOT N_PZ_1099 AND NOT aluopra(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_0 AND N_PZ_1129 AND N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND regd(0) AND NOT regfil_7_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_6_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND NOT regd(1) AND NOT regd(0) AND NOT regfil_4_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND NOT regfil_3_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND NOT regfil_2_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND NOT regfil_1_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_0_0)));
</td></tr><tr><td>
FDCPE_aluopra1: FDCPE port map (aluopra(1),aluopra_D(1),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;aluopra_D(1) <= NOT (((NOT aluopra(1) AND NOT N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_1 AND N_PZ_1129 AND N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND regd(0) AND NOT regfil_7_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_6_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND NOT regd(1) AND NOT regd(0) AND NOT regfil_4_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND NOT regfil_3_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND NOT regfil_2_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND NOT regfil_1_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_0_1)));
</td></tr><tr><td>
FDCPE_aluopra2: FDCPE port map (aluopra(2),aluopra_D(2),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;aluopra_D(2) <= NOT (((NOT N_PZ_1099 AND NOT aluopra(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1129 AND NOT regfil_5_2 AND N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND regd(0) AND NOT regfil_7_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_6_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND NOT regd(1) AND NOT regd(0) AND NOT regfil_4_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND NOT regfil_3_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_2_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND NOT regfil_1_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_0_2)));
</td></tr><tr><td>
FDCPE_aluopra3: FDCPE port map (aluopra(3),aluopra_D(3),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;aluopra_D(3) <= NOT (((NOT N_PZ_1099 AND NOT aluopra(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_3 AND N_PZ_1129 AND N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND regd(0) AND NOT regfil_7_3 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_6_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_3_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_2_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_1_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_0_3)));
</td></tr><tr><td>
FDCPE_aluopra4: FDCPE port map (aluopra(4),aluopra_D(4),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;aluopra_D(4) <= NOT (((NOT N_PZ_1099 AND NOT aluopra(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1129 AND N_PZ_1099 AND NOT regfil_5_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_7_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_6_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_3_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_2_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_1_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_0_4)));
</td></tr><tr><td>
FDCPE_aluopra5: FDCPE port map (aluopra(5),aluopra_D(5),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;aluopra_D(5) <= NOT (((NOT N_PZ_1099 AND NOT aluopra(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1129 AND N_PZ_1099 AND NOT regfil_5_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_7_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_6_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_3_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_2_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_1_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_0_5)));
</td></tr><tr><td>
FDCPE_aluopra6: FDCPE port map (aluopra(6),aluopra_D(6),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;aluopra_D(6) <= NOT (((NOT N_PZ_1099 AND NOT aluopra(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1129 AND N_PZ_1099 AND NOT regfil_5_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_7_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_6_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_3_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_2_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_1_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_0_6)));
</td></tr><tr><td>
FDCPE_aluopra7: FDCPE port map (aluopra(7),aluopra_D(7),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;aluopra_D(7) <= NOT (((NOT N_PZ_1099 AND NOT aluopra(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_7 AND N_PZ_1129 AND N_PZ_1099)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_7_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_6_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_3_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_2_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_1_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_0_7)));
</td></tr><tr><td>
FTCPE_aluoprb0: FTCPE port map (aluoprb(0),aluoprb_T(0),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;aluoprb_T(0) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	aluoprb(0) AND _COND_18(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT aluoprb(0) AND NOT _COND_18(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND data(0).PIN AND NOT regd(2) AND NOT regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regd(0) AND NOT aluoprb(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT data(0).PIN AND NOT regd(2) AND NOT regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regd(0) AND aluoprb(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND NOT aluoprb(0)));
</td></tr><tr><td>
FTCPE_aluoprb1: FTCPE port map (aluoprb(1),aluoprb_T(1),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;aluoprb_T(1) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	aluoprb(1) AND _COND_18(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT aluoprb(1) AND NOT _COND_18(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND data(0).PIN AND NOT regd(2) AND NOT regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND NOT aluoprb(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT data(0).PIN AND NOT regd(2) AND NOT regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND aluoprb(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND aluoprb(1)));
</td></tr><tr><td>
FTCPE_aluoprb2: FTCPE port map (aluoprb(2),aluoprb_T(2),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;aluoprb_T(2) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	aluoprb(2) AND _COND_18(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT aluoprb(2) AND NOT _COND_18(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND data(0).PIN AND NOT regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regd(0) AND NOT aluoprb(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT data(0).PIN AND NOT regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regd(0) AND aluoprb(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND aluoprb(2)));
</td></tr><tr><td>
FTCPE_aluoprb3: FTCPE port map (aluoprb(3),aluoprb_T(3),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;aluoprb_T(3) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	aluoprb(3) AND _COND_18(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT aluoprb(3) AND NOT _COND_18(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND data(0).PIN AND NOT regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND NOT aluoprb(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT data(0).PIN AND NOT regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND aluoprb(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND aluoprb(3)));
</td></tr><tr><td>
FTCPE_aluoprb4: FTCPE port map (aluoprb(4),aluoprb_T(4),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;aluoprb_T(4) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	aluoprb(4) AND _COND_18(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT aluoprb(4) AND NOT _COND_18(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND data(0).PIN AND regd(2) AND NOT regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regd(0) AND NOT aluoprb(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT data(0).PIN AND regd(2) AND NOT regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regd(0) AND aluoprb(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND aluoprb(4)));
</td></tr><tr><td>
FTCPE_aluoprb5: FTCPE port map (aluoprb(5),aluoprb_T(5),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;aluoprb_T(5) <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND data(0).PIN AND N_PZ_1129 AND NOT aluoprb(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT data(0).PIN AND N_PZ_1129 AND aluoprb(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	aluoprb(5) AND _COND_18(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT aluoprb(5) AND NOT _COND_18(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND aluoprb(5)));
</td></tr><tr><td>
FTCPE_aluoprb6: FTCPE port map (aluoprb(6),aluoprb_T(6),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;aluoprb_T(6) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	aluoprb(6) AND _COND_18(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT aluoprb(6) AND NOT _COND_18(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND data(0).PIN AND regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regd(0) AND NOT aluoprb(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT data(0).PIN AND regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regd(0) AND aluoprb(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND aluoprb(6)));
</td></tr><tr><td>
FTCPE_aluoprb7: FTCPE port map (aluoprb(7),aluoprb_T(7),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;aluoprb_T(7) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	aluoprb(7) AND _COND_18(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT aluoprb(7) AND NOT _COND_18(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND data(0).PIN AND NOT aluoprb(7) AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(1) AND regd(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT data(0).PIN AND aluoprb(7) AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(1) AND regd(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND aluoprb(7)));
</td></tr><tr><td>
FDCPE_alupar: FDCPE port map (alupar,alupar_D,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;alupar_D <= N_PZ_1261
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((m1/Mmux__old_resi_28_I3_Result28 AND NOT N_PZ_1997)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1527 AND NOT N_PZ_1997)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT m1/Mmux__old_resi_28_I3_Result28 AND N_PZ_1527 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1997));
</td></tr><tr><td>
FDCPE_alures0: FDCPE port map (alures(0),alures_D(0),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;alures_D(0) <= NOT (((NOT alusel(2) AND NOT m1/Mmux__old_resi_28_I7_Result30)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT m1/Mmux__old_resi_28_I7_Result30 AND NOT N_PZ_1076 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT aluoprb(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND alusel(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__old_resi_28_I7_Result30 AND NOT aluopra(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__old_resi_28_I7_Result30 AND NOT N_PZ_1076)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND NOT alusel(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__old_resi_28_I7_Result30 AND N_PZ_1076)));
</td></tr><tr><td>
FDCPE_alures1: FDCPE port map (alures(1),alures_D(1),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;alures_D(1) <= NOT (((NOT alusel(2) AND NOT m1/Mmux__old_resi_28_I6_Result28)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT m1/Mmux__old_resi_28_I6_Result28 AND NOT N_PZ_1043 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT aluoprb(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND alusel(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__old_resi_28_I6_Result28 AND NOT aluopra(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__old_resi_28_I6_Result28 AND NOT N_PZ_1043)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND NOT alusel(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__old_resi_28_I6_Result28 AND N_PZ_1043)));
</td></tr><tr><td>
FDCPE_alures2: FDCPE port map (alures(2),N_PZ_1213,clock,'0','0','1');
</td></tr><tr><td>
FDCPE_alures3: FDCPE port map (alures(3),N_PZ_1260,clock,'0','0','1');
</td></tr><tr><td>
FDCPE_alures4: FDCPE port map (alures(4),alures_D(4),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;alures_D(4) <= NOT ((NOT m1/Mmux__old_resi_28_I3_Result28 AND N_PZ_1527));
</td></tr><tr><td>
FDCPE_alures5: FDCPE port map (alures(5),N_PZ_1141,clock,'0','0','1');
</td></tr><tr><td>
FDCPE_alures6: FDCPE port map (alures(6),N_PZ_1261,clock,'0','0','1');
</td></tr><tr><td>
FDCPE_alures7: FDCPE port map (alures(7),N_PZ_1214,clock,'0','0','1');
</td></tr><tr><td>
FTCPE_alusel0: FTCPE port map (alusel(0),alusel_T(0),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;alusel_T(0) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND NOT alusel(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND alusel(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND alusel(0)));
</td></tr><tr><td>
FTCPE_alusel1: FTCPE port map (alusel(1),alusel_T(1),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;alusel_T(1) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND NOT alusel(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND alusel(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND alusel(1)));
</td></tr><tr><td>
FTCPE_alusel2: FTCPE port map (alusel(2),alusel_T(2),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;alusel_T(2) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND NOT alusel(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND alusel(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND alusel(2)));
</td></tr><tr><td>
FDCPE_aluzout: FDCPE port map (aluzout,aluzout_D,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;aluzout_D <= ((NOT alusel(2) AND NOT m1/Mmux__old_resi_28_I7_Result30 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__old_resi_28_I6_Result28 AND NOT N_PZ_1213 AND NOT N_PZ_1260 AND NOT N_PZ_1141 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__old_resi_28_I3_Result28 AND NOT N_PZ_1214 AND NOT N_PZ_1261)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT m1/Mmux__old_resi_28_I7_Result30 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__old_resi_28_I6_Result28 AND NOT N_PZ_1213 AND NOT N_PZ_1260 AND NOT N_PZ_1141 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__old_resi_28_I3_Result28 AND NOT N_PZ_1214 AND NOT N_PZ_1261 AND N_PZ_1527 AND N_PZ_1954));
</td></tr><tr><td>
FTCPE_auxcar: FTCPE port map (auxcar,auxcar_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;auxcar_T <= ((auxcar AND N_PZ_1894)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND auxcar AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1986)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND NOT auxcar AND NOT N_PZ_1986));
</td></tr><tr><td>
FTCPE_carry: FTCPE port map (carry,carry_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;carry_T <= ((NOT reset AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT carry AND _mux000762)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT carry AND alucout)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND carry AND NOT alucout AND NOT _mux000762)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _mux000762)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _mux000762)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND NOT N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _mux000762));
</td></tr><tr><td>
FDCPE_carryhold: FDCPE port map (carryhold,regfil_7_0,clock,'0','0',carryhold_CE);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;carryhold_CE <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT data(5).PIN);
</td></tr><tr><td>
FTCPE_dataeno: FTCPE port map (dataeno,dataeno_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;dataeno_T <= ((reset AND dataeno)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT dataeno)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (state(3) AND state(2) AND state(4) AND NOT state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0) AND dataeno)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (state(3) AND NOT state(2) AND NOT state(4) AND NOT state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0) AND dataeno)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT dataeno));
</td></tr><tr><td>
FTCPE_holding0: FTCPE port map (holding(0),holding_T(0),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;holding_T(0) <= ((holding(0) AND NOT regfil_4_0 AND N_PZ_2114)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT holding(0) AND regfil_4_0 AND N_PZ_2114)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND holding(0) AND NOT regfil_7_0 AND auxcar)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND holding(0) AND NOT regfil_7_0 AND NOT N_PZ_1986)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND NOT holding(0) AND regfil_7_0 AND auxcar)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND NOT holding(0) AND regfil_7_0 AND NOT N_PZ_1986));
</td></tr><tr><td>
FTCPE_holding1: FTCPE port map (holding(1),holding_T(1),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;holding_T(1) <= ((holding(1) AND NOT regfil_4_1 AND N_PZ_2114)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT holding(1) AND regfil_4_1 AND N_PZ_2114)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_7_1 AND holding(1) AND regfil_7_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_7_1 AND holding(1) AND auxcar)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND NOT regfil_7_1 AND NOT holding(1) AND auxcar)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND NOT regfil_7_1 AND NOT holding(1) AND regfil_7_3 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_7_2));
</td></tr><tr><td>
FTCPE_holding2: FTCPE port map (holding(2),holding_T(2),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;holding_T(2) <= ((holding(2) AND NOT regfil_4_2 AND N_PZ_2114)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT holding(2) AND regfil_4_2 AND N_PZ_2114)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_7_3 AND holding(2) AND N_PZ_1890)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND holding(2) AND auxcar AND N_PZ_1890)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND NOT holding(2) AND auxcar AND NOT N_PZ_1890)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_7_3 AND regfil_7_2 AND NOT holding(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1890));
</td></tr><tr><td>
FTCPE_holding3: FTCPE port map (holding(3),holding_T(3),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;holding_T(3) <= ((N_PZ_2114 AND holding(3) AND NOT regfil_4_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT holding(3) AND regfil_4_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND holding(3) AND NOT N_PZ_1986)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_7_1 AND NOT regfil_7_3 AND NOT holding(3) AND auxcar)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND NOT regfil_7_3 AND regfil_7_2 AND NOT holding(3) AND auxcar)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND NOT regfil_7_1 AND regfil_7_3 AND NOT regfil_7_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT holding(3) AND auxcar)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND NOT regfil_7_1 AND NOT regfil_7_3 AND NOT regfil_7_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	holding(3) AND auxcar));
</td></tr><tr><td>
FTCPE_holding4: FTCPE port map (holding(4),holding_T(4),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;holding_T(4) <= ((N_PZ_2114 AND holding(4) AND NOT regfil_4_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT holding(4) AND regfil_4_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND holding(4) AND NOT regfil_7_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND NOT holding(4) AND regfil_7_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND holding(4) AND NOT regfil_7_4 AND regfil_7_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1887)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND NOT holding(4) AND regfil_7_4 AND regfil_7_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1887));
</td></tr><tr><td>
FTCPE_holding5: FTCPE port map (holding(5),holding_T(5),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;holding_T(5) <= ((N_PZ_2114 AND regfil_4_5 AND NOT holding(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT regfil_4_5 AND holding(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_7_5 AND holding(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND NOT regfil_7_5 AND NOT holding(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_7_5 AND regfil_7_7 AND holding(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND NOT regfil_7_5 AND regfil_7_6 AND regfil_7_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT holding(5)));
</td></tr><tr><td>
FTCPE_holding6: FTCPE port map (holding(6),holding_T(6),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;holding_T(6) <= ((N_PZ_2114 AND regfil_4_6 AND NOT holding(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT regfil_4_6 AND holding(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND N_PZ_1887 AND NOT holding(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_7_5 AND regfil_7_6 AND NOT holding(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_7_5 AND NOT regfil_7_6 AND holding(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND NOT regfil_7_5 AND regfil_7_6 AND holding(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_7_5 AND regfil_7_6 AND regfil_7_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT holding(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_7_5 AND NOT regfil_7_6 AND regfil_7_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	holding(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND NOT regfil_7_5 AND regfil_7_6 AND regfil_7_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	holding(6)));
</td></tr><tr><td>
FTCPE_holding7: FTCPE port map (holding(7),holding_T(7),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;holding_T(7) <= ((N_PZ_2114 AND holding(7) AND NOT regfil_4_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT holding(7) AND regfil_4_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_7_7 AND holding(7) AND NOT N_PZ_1887)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_7_7 AND NOT holding(7) AND N_PZ_1887)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND NOT regfil_7_7 AND holding(7) AND N_PZ_1887)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND NOT regfil_7_7 AND NOT holding(7) AND NOT N_PZ_1887));
</td></tr><tr><td>
</td></tr><tr><td>
m1/Madd__addsub0000__or0000 <= ((aluoprb(1) AND aluopra(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1076 AND N_PZ_1043 AND aluopra(0)));
</td></tr><tr><td>
</td></tr><tr><td>
m1/Mmux__mux0000_Result1 <= ((NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND aluoprb(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/_addsub0000(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND aluopra(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/_addsub0000(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND aluoprb(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1076 AND aluopra(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND aluoprb(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1043 AND aluopra(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND aluoprb(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/_addsub0000(2) AND aluopra(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND aluoprb(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/_addsub0000(3) AND aluopra(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND aluoprb(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/_addsub0000(4) AND aluopra(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND aluoprb(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	aluopra(7) AND NOT m1/_addsub0000(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND aluoprb(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	aluopra(7) AND NOT m1/_addsub0000(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND aluoprb(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	aluopra(7) AND NOT alucin)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND NOT aluoprb(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1076 AND N_PZ_1043 AND m1/_addsub0000(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/_addsub0000(3) AND m1/_addsub0000(4) AND aluopra(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/_addsub0000(6) AND m1/_addsub0000(5) AND alucin)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND N_PZ_1076 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1043 AND m1/_addsub0000(2) AND m1/_addsub0000(3) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/_addsub0000(4) AND NOT aluopra(7) AND m1/_addsub0000(6) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/_addsub0000(5) AND alucin AND m1/_addsub0000(7)));
</td></tr><tr><td>
</td></tr><tr><td>
m1/Mmux__mux0000_Result3 <= ((alusel(1) AND alusel(0) AND NOT alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/Msub__AUX_23__xor0019 AND NOT N_PZ_1092)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND alusel(0) AND NOT alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/Msub__AUX_23__xor0019 AND NOT aluopra(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND alusel(0) AND NOT alusel(2) AND N_PZ_1092 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT aluopra(7) AND m1/Msub__AUX_23__xor0016)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND alusel(0) AND NOT alusel(2) AND N_PZ_1092 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT aluopra(7) AND m1/Msub__AUX_23__xor0013)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND alusel(0) AND NOT alusel(2) AND N_PZ_1092 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT aluopra(7) AND m1/Msub__AUX_23__xor0010)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND alusel(0) AND NOT alusel(2) AND N_PZ_1092 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT aluopra(7) AND NOT N_PZ_1999)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(2) AND NOT N_PZ_1092 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Msub__AUX_23__xor0016 AND NOT m1/Msub__AUX_23__xor0013 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Msub__AUX_23__xor0010 AND N_PZ_1999)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(2) AND NOT aluoprb(7) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Msub__AUX_23__xor0019 AND NOT m1/Msub__AUX_23__xor0016 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Msub__AUX_23__xor0013 AND NOT m1/Msub__AUX_23__xor0010 AND N_PZ_1999));
</td></tr><tr><td>
</td></tr><tr><td>
m1/Mmux__old_resi_28_I3_Result28 <= (NOT alusel(1) AND m1/_addsub0000(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((alusel(1) AND NOT alusel(2) AND m1/Msub__AUX_23__xor0010 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1999)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(2) AND NOT m1/Msub__AUX_23__xor0010 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1999)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__old_resi_28_I7_Result30 AND m1/_addsub0000(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND NOT alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__old_resi_28_I7_Result30 AND N_PZ_1076 AND N_PZ_1043 AND m1/_addsub0000(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/_addsub0000(3)));
</td></tr><tr><td>
</td></tr><tr><td>
m1/Mmux__old_resi_28_I6_Result28 <= (NOT alusel(2) AND N_PZ_1043)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((alusel(1) AND NOT alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/Mmux__old_resi_28_I7_Result30 AND NOT N_PZ_1076)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(2) AND N_PZ_1076 AND NOT aluopra(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND m1/Mmux__old_resi_28_I7_Result30 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1076 AND NOT N_PZ_1043)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND NOT alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__old_resi_28_I7_Result30 AND N_PZ_1076)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND NOT alusel(2) AND NOT N_PZ_1076 AND aluopra(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/Mmux__old_resi_28_I7_Result30 AND N_PZ_1076 AND N_PZ_1043));
</td></tr><tr><td>
</td></tr><tr><td>
m1/Mmux__old_resi_28_I7_Result30 <= (NOT alusel(2) AND N_PZ_1076)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR (alusel(0) AND NOT alusel(2) AND alucin);
</td></tr><tr><td>
</td></tr><tr><td>
m1/Msub__AUX_23__xor0007 <= ((aluoprb(2) AND NOT N_PZ_1082 AND NOT aluopra(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT aluoprb(2) AND N_PZ_1082 AND aluopra(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1082 AND NOT m1/Msub__sub0000__or0001 AND N_PZ_1041)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1082 AND m1/Msub__sub0000__or0001 AND N_PZ_1041));
</td></tr><tr><td>
</td></tr><tr><td>
m1/Msub__AUX_23__xor0010 <= ((aluoprb(3) AND NOT N_PZ_1054 AND NOT aluopra(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT aluoprb(3) AND N_PZ_1054 AND aluopra(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1054 AND NOT N_PZ_1082 AND NOT m1/Msub__AUX_23__xor0007)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1054 AND NOT N_PZ_1082 AND m1/Msub__AUX_23__xor0007));
</td></tr><tr><td>
</td></tr><tr><td>
m1/Msub__AUX_23__xor0013 <= N_PZ_1038
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((NOT aluopra(4) AND N_PZ_1054)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1054 AND m1/Msub__AUX_23__xor0010));
</td></tr><tr><td>
</td></tr><tr><td>
m1/Msub__AUX_23__xor0016 <= ((aluoprb(5) AND NOT aluopra(5) AND NOT N_PZ_1059)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT aluoprb(5) AND aluopra(5) AND N_PZ_1059)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1059 AND NOT m1/Msub__AUX_23__xor0013 AND NOT N_PZ_1038)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1059 AND m1/Msub__AUX_23__xor0013 AND NOT N_PZ_1038));
</td></tr><tr><td>
</td></tr><tr><td>
m1/Msub__AUX_23__xor0019 <= N_PZ_1092
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	XOR ((m1/Msub__AUX_23__xor0016 AND NOT N_PZ_1059)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1059 AND NOT aluopra(6)));
</td></tr><tr><td>
</td></tr><tr><td>
m1/Msub__sub0000__or0001 <= ((aluoprb(1) AND NOT aluopra(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (aluoprb(0) AND NOT N_PZ_1043 AND NOT aluopra(0)));
</td></tr><tr><td>
</td></tr><tr><td>
m1/Mxor__xor0001_Mxor__xor0000__xor0001 <= ((m1/Mmux__old_resi_28_I7_Result30 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/Mmux__old_resi_28_I6_Result28)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(2) AND NOT m1/Mmux__old_resi_28_I7_Result30 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__old_resi_28_I6_Result28)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT m1/Mmux__old_resi_28_I7_Result30 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Mmux__old_resi_28_I6_Result28 AND N_PZ_1954)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/Mmux__old_resi_28_I7_Result30 AND aluopra(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/Mmux__old_resi_28_I6_Result28 AND aluopra(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND alusel(2) AND aluopra(1) AND aluopra(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(0) AND alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/Mmux__old_resi_28_I7_Result30 AND N_PZ_1043)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(0) AND alusel(2) AND N_PZ_1076 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/Mmux__old_resi_28_I6_Result28)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(0) AND alusel(2) AND N_PZ_1076 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	aluopra(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alusel(1) AND NOT alusel(0) AND alusel(2) AND N_PZ_1043 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	aluopra(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/Mmux__old_resi_28_I7_Result30 AND N_PZ_1043)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND alusel(2) AND N_PZ_1076 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/Mmux__old_resi_28_I6_Result28)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(1) AND alusel(0) AND alusel(2) AND N_PZ_1076 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1043)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(0) AND alusel(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/Mmux__old_resi_28_I7_Result30 AND NOT N_PZ_1043 AND aluopra(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(0) AND alusel(2) AND NOT N_PZ_1076 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	m1/Mmux__old_resi_28_I6_Result28 AND aluopra(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(0) AND alusel(2) AND aluoprb(0) AND aluoprb(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT m1/Msub__sub0000__or0001)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT alusel(0) AND NOT m1/Mmux__old_resi_28_I7_Result30 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1076 AND NOT m1/Mmux__old_resi_28_I6_Result28 AND N_PZ_1043));
</td></tr><tr><td>
</td></tr><tr><td>
m1/_addsub0000(2) <= ((m1/Madd__addsub0000__or0000 AND N_PZ_1041)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT m1/Madd__addsub0000__or0000 AND NOT N_PZ_1041));
</td></tr><tr><td>
</td></tr><tr><td>
m1/_addsub0000(3) <= ((m1/Madd__addsub0000__or0000 AND NOT N_PZ_1082 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1041)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT m1/Madd__addsub0000__or0000 AND N_PZ_1082 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1041)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (aluoprb(2) AND NOT N_PZ_1082 AND aluopra(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT aluoprb(2) AND N_PZ_1082 AND NOT aluopra(2)));
</td></tr><tr><td>
</td></tr><tr><td>
m1/_addsub0000(4) <= ((m1/_addsub0000(3) AND N_PZ_1054 AND N_PZ_1082)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT m1/_addsub0000(3) AND NOT N_PZ_1054 AND N_PZ_1082)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (aluoprb(3) AND NOT N_PZ_1054 AND aluopra(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT aluoprb(3) AND N_PZ_1054 AND NOT aluopra(3)));
</td></tr><tr><td>
</td></tr><tr><td>
m1/_addsub0000(5) <= ((m1/_addsub0000(4) AND N_PZ_1038 AND N_PZ_1054)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT m1/_addsub0000(4) AND NOT N_PZ_1038 AND N_PZ_1054)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1038 AND NOT N_PZ_1054 AND NOT aluoprb(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1038 AND aluopra(4) AND NOT N_PZ_1054));
</td></tr><tr><td>
</td></tr><tr><td>
m1/_addsub0000(6) <= ((aluoprb(5) AND aluopra(5) AND NOT N_PZ_1059)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT aluoprb(5) AND NOT aluopra(5) AND N_PZ_1059)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1059 AND N_PZ_1038 AND m1/_addsub0000(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1059 AND N_PZ_1038 AND NOT m1/_addsub0000(5)));
</td></tr><tr><td>
</td></tr><tr><td>
m1/_addsub0000(7) <= ((N_PZ_1092 AND N_PZ_1059 AND m1/_addsub0000(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1092 AND NOT N_PZ_1059 AND NOT aluoprb(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1092 AND N_PZ_1059 AND NOT m1/_addsub0000(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1092 AND NOT N_PZ_1059 AND aluopra(6)));
</td></tr><tr><td>
FDCPE_parity: FDCPE port map (parity,parity_D,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;parity_D <= ((N_PZ_1894 AND alupar)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1894 AND parity));
</td></tr><tr><td>
FDCPE_pc0: FDCPE port map (pc(0),pc_D(0),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;pc_D(0) <= ((NOT N_PZ_1209 AND pc(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1145 AND NOT pc(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_5_0));
</td></tr><tr><td>
FDCPE_pc1: FDCPE port map (pc(1),pc_D(1),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;pc_D(1) <= ((NOT N_PZ_1209 AND pc(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1145 AND pc(0) AND NOT pc(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT N_PZ_1891 AND NOT pc(0) AND pc(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_5_1));
</td></tr><tr><td>
FTCPE_pc2: FTCPE port map (pc(2),pc_T(2),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;pc_T(2) <= ((reset AND pc(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1117 AND pc(0) AND pc(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND data(1).PIN AND N_PZ_2033)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT N_PZ_1916 AND N_PZ_2033)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT regfil_5_2 AND N_PZ_2033)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND N_PZ_2236 AND pc(0) AND pc(1) AND NOT pc(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(6).PIN AND data(7).PIN AND pc(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND N_PZ_1916 AND NOT regfil_5_2 AND pc(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_5_2 AND NOT pc(2)));
</td></tr><tr><td>
FDCPE_pc3: FDCPE port map (pc(3),pc_D(3),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;pc_D(3) <= ((NOT N_PZ_1209 AND pc(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1145 AND pc(3) AND NOT N_PZ_2033)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1145 AND NOT pc(3) AND N_PZ_2033)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_5_3));
</td></tr><tr><td>
FTCPE_pc4: FTCPE port map (pc(4),pc_T(4),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;pc_T(4) <= ((reset AND pc(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1117 AND pc(3) AND N_PZ_2033)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(2).PIN AND data(1).PIN AND pc(3) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2033)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(1).PIN AND NOT N_PZ_1916 AND pc(3) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2033)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND N_PZ_1916 AND pc(3) AND NOT regfil_5_4 AND pc(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2033)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT data(4).PIN AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND data(6).PIN AND data(7).PIN AND pc(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND N_PZ_1916 AND NOT regfil_5_4 AND pc(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND NOT pc(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(6).PIN AND data(7).PIN AND N_PZ_1916 AND regfil_5_4 AND NOT pc(4)));
</td></tr><tr><td>
FDCPE_pc5: FDCPE port map (pc(5),pc_D(5),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;pc_D(5) <= ((NOT N_PZ_1209 AND pc(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1145 AND NOT pc(4) AND pc(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1145 AND NOT pc(3) AND pc(4) AND pc(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1145 AND pc(3) AND pc(4) AND N_PZ_2033 AND NOT pc(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1145 AND pc(3) AND pc(4) AND NOT N_PZ_2033 AND pc(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND data(6).PIN AND data(7).PIN AND data(5).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_5_5));
</td></tr><tr><td>
FTCPE_pc6: FTCPE port map (pc(6),pc_T(6),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;pc_T(6) <= ((reset AND pc(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1117 AND pc(3) AND pc(4) AND N_PZ_2033 AND pc(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(6).PIN AND data(7).PIN AND pc(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT N_PZ_1916 AND pc(3) AND pc(6) AND pc(4) AND N_PZ_2033 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	pc(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND pc(3) AND NOT regfil_5_6 AND pc(6) AND pc(4) AND N_PZ_2033 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	pc(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(2).PIN AND data(1).PIN AND pc(3) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	pc(4) AND N_PZ_2033 AND pc(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(1).PIN AND NOT N_PZ_1916 AND pc(3) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	pc(4) AND N_PZ_2033 AND pc(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND N_PZ_1916 AND NOT regfil_5_6 AND pc(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_5_6 AND NOT pc(6)));
</td></tr><tr><td>
FDCPE_pc7: FDCPE port map (pc(7),pc_D(7),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;pc_D(7) <= ((NOT N_PZ_1209 AND pc(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (pc(7) AND N_PZ_1145 AND NOT N_PZ_2021)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1145 AND NOT N_PZ_2021 AND pc(3) AND pc(6) AND pc(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2033 AND pc(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_5_7));
</td></tr><tr><td>
FTCPE_pc8: FTCPE port map (pc(8),pc_T(8),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;pc_T(8) <= ((reset AND pc(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1117 AND N_PZ_2021)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND data(1).PIN AND N_PZ_2021 AND pc(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT N_PZ_1916 AND N_PZ_2021 AND pc(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND N_PZ_2021 AND NOT regfil_4_0 AND pc(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND N_PZ_2236 AND N_PZ_2021 AND NOT pc(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(6).PIN AND data(7).PIN AND pc(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND N_PZ_1916 AND NOT regfil_4_0 AND pc(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_4_0 AND NOT pc(8)));
</td></tr><tr><td>
FDCPE_pc9: FDCPE port map (pc(9),pc_D(9),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;pc_D(9) <= ((NOT N_PZ_1209 AND pc(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1145 AND NOT pc(8) AND pc(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1145 AND N_PZ_2021 AND pc(8) AND NOT pc(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1145 AND NOT N_PZ_2021 AND pc(8) AND pc(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_4_1));
</td></tr><tr><td>
FTCPE_pc10: FTCPE port map (pc(10),pc_T(10),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;pc_T(10) <= ((reset AND pc(10))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1117 AND N_PZ_2021 AND pc(8) AND pc(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT N_PZ_1916 AND N_PZ_2021 AND pc(10) AND pc(8) AND pc(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND N_PZ_2021 AND NOT regfil_4_2 AND pc(10) AND pc(8) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	pc(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2021 AND pc(8) AND pc(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(1).PIN AND NOT N_PZ_1916 AND N_PZ_2021 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	pc(8) AND pc(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND data(2).PIN AND data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(6).PIN AND data(7).PIN AND pc(10))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND N_PZ_1916 AND NOT regfil_4_2 AND pc(10))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_4_2 AND NOT pc(10)));
</td></tr><tr><td>
FDCPE_pc11: FDCPE port map (pc(11),pc_D(11),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;pc_D(11) <= ((NOT N_PZ_1209 AND pc(11))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND pc(11) AND NOT N_PZ_1223 AND NOT N_PZ_1891)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND N_PZ_1209 AND N_PZ_2021 AND pc(10) AND pc(8) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	pc(9) AND NOT N_PZ_1223 AND NOT N_PZ_1891)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND NOT data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(6).PIN AND data(7).PIN AND N_PZ_1209 AND N_PZ_1916 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_4_3));
</td></tr><tr><td>
FDCPE_pc12: FDCPE port map (pc(12),pc_D(12),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;pc_D(12) <= ((NOT N_PZ_1209 AND pc(12))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT N_PZ_1223 AND NOT N_PZ_1891 AND pc(12))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND N_PZ_1209 AND N_PZ_1223 AND NOT N_PZ_1891 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT pc(12))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1209 AND N_PZ_1819 AND regfil_4_4));
</td></tr><tr><td>
FDCPE_pc13: FDCPE port map (pc(13),pc_D(13),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;pc_D(13) <= ((pc(13) AND NOT N_PZ_2067)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1145 AND N_PZ_1223 AND pc(12) AND NOT pc(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_4_5));
</td></tr><tr><td>
FDCPE_pc14: FDCPE port map (pc(14),pc_D(14),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;pc_D(14) <= ((NOT N_PZ_2067 AND pc(14))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1145 AND NOT pc(13) AND pc(14))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1145 AND N_PZ_1223 AND pc(12) AND pc(13) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT pc(14))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_4_6));
</td></tr><tr><td>
FDCPE_pc15: FDCPE port map (pc(15),pc_D(15),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;pc_D(15) <= ((NOT N_PZ_2067 AND pc(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1145 AND NOT pc(13) AND pc(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1145 AND NOT pc(14) AND pc(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1145 AND N_PZ_1223 AND pc(12) AND pc(13) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	pc(14) AND NOT pc(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND regfil_4_7));
</td></tr><tr><td>
FTCPE_regd0: FTCPE port map (regd(0),regd_T(0),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regd_T(0) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND NOT regd(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT regd(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND NOT data(7).PIN AND NOT regd(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND NOT data(7).PIN AND regd(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT _cmp_eq0004 AND regd(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(7).PIN AND NOT regd(0) AND NOT N_PZ_1916)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(7).PIN AND NOT _cmp_eq0004 AND regd(0)));
</td></tr><tr><td>
FTCPE_regd1: FTCPE port map (regd(1),regd_T(1),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regd_T(1) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND NOT regd(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND NOT data(6).PIN AND NOT regd(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT regd(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT _cmp_eq0004 AND NOT regd(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT _cmp_eq0004 AND regd(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND regd(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND regd(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT N_PZ_1819 AND NOT regd(1)));
</td></tr><tr><td>
FTCPE_regd2: FTCPE port map (regd(2),regd_T(2),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regd_T(2) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND NOT regd(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND data(5).PIN AND NOT regd(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND NOT data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND data(5).PIN AND NOT regd(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND NOT regd(2) AND NOT _cmp_eq0004)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regd(2) AND NOT _cmp_eq0004)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND NOT data(5).PIN AND regd(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND NOT data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN AND NOT data(5).PIN AND regd(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT regd(2) AND NOT N_PZ_1819));
</td></tr><tr><td>
FTCPE_regfil_0_0: FTCPE port map (regfil_0_0,regfil_0_0_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_0_0_T <= ((NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1268 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_0_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND NOT N_PZ_1268 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1996 AND NOT regfil_0_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND addrhold(7) AND NOT regfil_0_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT addrhold(7) AND regfil_0_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_1_0 AND regfil_1_2 AND regfil_1_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_1_3 AND regfil_1_6 AND regfil_1_4 AND regfil_1_5 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_1_7));
</td></tr><tr><td>
FTCPE_regfil_0_1: FTCPE port map (regfil_0_1,regfil_0_1_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_0_1_T <= ((NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1262 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_0_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1946 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_0_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND addrhold(8) AND NOT regfil_0_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT addrhold(8) AND regfil_0_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_1_0 AND regfil_1_2 AND regfil_1_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_1_3 AND regfil_1_6 AND regfil_1_4 AND regfil_1_5 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_1_7 AND regfil_0_0));
</td></tr><tr><td>
FTCPE_regfil_0_2: FTCPE port map (regfil_0_2,regfil_0_2_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_0_2_T <= ((NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1944 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_0_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND regfil_0_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1945)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND addrhold(9) AND NOT regfil_0_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT addrhold(9) AND regfil_0_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_1_0 AND regfil_1_2 AND regfil_1_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_0_1 AND regfil_1_3 AND regfil_1_6 AND regfil_1_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_1_5 AND regfil_1_7 AND regfil_0_0));
</td></tr><tr><td>
FTCPE_regfil_0_3: FTCPE port map (regfil_0_3,regfil_0_3_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_0_3_T <= ((NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1943 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_0_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND regfil_0_3 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2180)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND addrhold(10) AND NOT regfil_0_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT addrhold(10) AND regfil_0_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_1_0 AND regfil_1_2 AND regfil_1_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_0_1 AND regfil_1_3 AND regfil_1_6 AND regfil_1_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_1_5 AND regfil_1_7 AND regfil_0_2 AND regfil_0_0));
</td></tr><tr><td>
FTCPE_regfil_0_4: FTCPE port map (regfil_0_4,regfil_0_4_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_0_4_T <= ((NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_2181 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_0_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1996 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_2181 AND NOT regfil_0_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND addrhold(11) AND NOT regfil_0_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT addrhold(11) AND regfil_0_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_1_0 AND regfil_1_2 AND regfil_1_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_0_1 AND regfil_1_3 AND regfil_1_6 AND regfil_1_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_0_3 AND regfil_1_5 AND regfil_1_7 AND regfil_0_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_0_0));
</td></tr><tr><td>
FTCPE_regfil_0_5: FTCPE port map (regfil_0_5,regfil_0_5_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_0_5_T <= ((N_PZ_1799)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1265 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_0_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_2000 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_0_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND addrhold(12) AND NOT regfil_0_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT addrhold(12) AND regfil_0_5));
</td></tr><tr><td>
FTCPE_regfil_0_6: FTCPE port map (regfil_0_6,regfil_0_6_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_0_6_T <= ((regfil_0_5 AND N_PZ_1799)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND regfil_0_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2106)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND NOT regfil_0_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1888)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND addrhold(13) AND NOT regfil_0_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT addrhold(13) AND regfil_0_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(6).PIN AND NOT regd(2) AND NOT regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regd(0) AND NOT regfil_0_6));
</td></tr><tr><td>
FTCPE_regfil_0_7: FTCPE port map (regfil_0_7,regfil_0_7_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_0_7_T <= ((regfil_0_5 AND N_PZ_1799 AND regfil_0_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1266 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_0_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_2001 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_0_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND addrhold(14) AND NOT regfil_0_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT addrhold(14) AND regfil_0_7));
</td></tr><tr><td>
FTCPE_regfil_1_0: FTCPE port map (regfil_1_0,regfil_1_0_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_1_0_T <= ((NOT regd(2) AND NOT regd(1) AND regd(0) AND regfil_1_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1268)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND NOT regfil_1_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1268 AND N_PZ_1996)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND addrhold(0) AND NOT regfil_1_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT addrhold(0) AND regfil_1_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN));
</td></tr><tr><td>
FTCPE_regfil_1_1: FTCPE port map (regfil_1_1,regfil_1_1_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_1_1_T <= ((NOT regd(2) AND NOT regd(1) AND regd(0) AND regfil_1_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1946)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND NOT regfil_1_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1262)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND addrhold(1) AND NOT regfil_1_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT addrhold(1) AND regfil_1_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_1_0));
</td></tr><tr><td>
FTCPE_regfil_1_2: FTCPE port map (regfil_1_2,regfil_1_2_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_1_2_T <= ((NOT regd(2) AND NOT regd(1) AND regd(0) AND regfil_1_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1945)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND NOT regfil_1_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1944)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND addrhold(2) AND NOT regfil_1_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT addrhold(2) AND regfil_1_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_1_0 AND regfil_1_1));
</td></tr><tr><td>
FTCPE_regfil_1_3: FTCPE port map (regfil_1_3,regfil_1_3_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_1_3_T <= ((NOT regd(2) AND NOT regd(1) AND regd(0) AND regfil_1_3 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2180)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND NOT regfil_1_3 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1943)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND addrhold(3) AND NOT regfil_1_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT addrhold(3) AND regfil_1_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_1_0 AND regfil_1_2 AND regfil_1_1));
</td></tr><tr><td>
FTCPE_regfil_1_4: FTCPE port map (regfil_1_4,regfil_1_4_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_1_4_T <= ((NOT regd(2) AND NOT regd(1) AND regd(0) AND regfil_1_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2181)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND N_PZ_1996 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_1_4 AND NOT N_PZ_2181)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND addrhold(4) AND NOT regfil_1_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT addrhold(4) AND regfil_1_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_1_0 AND regfil_1_2 AND regfil_1_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_1_3));
</td></tr><tr><td>
FTCPE_regfil_1_5: FTCPE port map (regfil_1_5,regfil_1_5_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_1_5_T <= ((NOT regd(2) AND NOT regd(1) AND regd(0) AND N_PZ_1265 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_1_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND regfil_1_5 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND addrhold(5) AND NOT regfil_1_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT addrhold(5) AND regfil_1_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_1_0 AND regfil_1_2 AND regfil_1_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_1_3 AND regfil_1_4));
</td></tr><tr><td>
FTCPE_regfil_1_6: FTCPE port map (regfil_1_6,regfil_1_6_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_1_6_T <= ((NOT state(3) AND state(1) AND NOT N_PZ_1066 AND NOT state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1209 AND addrhold(6) AND NOT regfil_1_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND state(1) AND NOT N_PZ_1066 AND NOT state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1209 AND NOT addrhold(6) AND regfil_1_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (state(3) AND state(2) AND NOT state(4) AND state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1209 AND NOT regd(2) AND NOT regd(1) AND regd(0) AND regfil_1_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT alures(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (state(3) AND state(2) AND NOT state(4) AND state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1209 AND NOT regd(2) AND NOT regd(1) AND regd(0) AND NOT regfil_1_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	alures(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND state(2) AND NOT state(4) AND NOT state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0) AND data(6).PIN AND NOT N_PZ_1209 AND NOT regd(2) AND NOT regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND NOT regfil_1_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND state(2) AND NOT state(4) AND NOT state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0) AND NOT data(6).PIN AND NOT N_PZ_1209 AND NOT regd(2) AND NOT regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND regfil_1_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1209 AND NOT regd(2) AND NOT _cmp_eq0004 AND NOT regd(1) AND regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1373 AND regfil_1_6 AND _COND_18(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1209 AND NOT regd(2) AND NOT _cmp_eq0004 AND NOT regd(1) AND regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1373 AND NOT regfil_1_6 AND NOT _COND_18(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND N_PZ_1209 AND regfil_1_0 AND regfil_1_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_1_1 AND regfil_1_3 AND regfil_1_4 AND regfil_1_5));
</td></tr><tr><td>
FTCPE_regfil_1_7: FTCPE port map (regfil_1_7,regfil_1_7_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_1_7_T <= ((NOT regd(2) AND NOT regd(1) AND regd(0) AND regfil_1_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2001)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND NOT regfil_1_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1266)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND addrhold(7) AND NOT regfil_1_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT addrhold(7) AND regfil_1_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_1_0 AND regfil_1_2 AND regfil_1_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_1_3 AND regfil_1_6 AND regfil_1_4 AND regfil_1_5));
</td></tr><tr><td>
FTCPE_regfil_2_0: FTCPE port map (regfil_2_0,regfil_2_0_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_2_0_T <= ((holding(0) AND NOT regfil_2_0 AND N_PZ_2114)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT holding(0) AND regfil_2_0 AND N_PZ_2114)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1268 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_2_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND NOT N_PZ_1268 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1996 AND NOT regfil_2_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND addrhold(7) AND NOT regfil_2_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT addrhold(7) AND regfil_2_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_3_0 AND regfil_3_1 AND regfil_3_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_3 AND regfil_3_4 AND regfil_3_5 AND N_PZ_1941 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_6 AND regfil_3_7));
</td></tr><tr><td>
FTCPE_regfil_2_1: FTCPE port map (regfil_2_1,regfil_2_1_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_2_1_T <= ((holding(1) AND N_PZ_2114 AND NOT regfil_2_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT holding(1) AND regfil_2_1 AND NOT N_PZ_2155)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND regfil_2_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1946)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND NOT regfil_2_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1262)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND addrhold(8) AND NOT regfil_2_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT addrhold(8) AND regfil_2_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_3_0 AND regfil_2_0 AND regfil_3_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_2 AND regfil_3_3 AND regfil_3_4 AND regfil_3_5 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1941 AND regfil_3_6 AND regfil_3_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_3_0 AND NOT holding(1) AND regfil_2_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2114 AND regfil_3_1 AND regfil_2_1 AND regfil_3_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_3 AND regfil_3_4 AND regfil_3_5 AND regfil_3_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_7));
</td></tr><tr><td>
FTCPE_regfil_2_2: FTCPE port map (regfil_2_2,regfil_2_2_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_2_2_T <= ((holding(2) AND N_PZ_2114 AND NOT regfil_2_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT holding(2) AND regfil_2_2 AND NOT N_PZ_2155)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1944 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_2_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND regfil_2_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1945)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND addrhold(9) AND NOT regfil_2_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT addrhold(9) AND regfil_2_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_3_0 AND regfil_2_0 AND regfil_3_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_2_1 AND regfil_3_2 AND regfil_3_3 AND regfil_3_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_5 AND N_PZ_1941 AND regfil_3_6 AND regfil_3_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_3_0 AND NOT holding(2) AND regfil_2_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2114 AND regfil_3_1 AND regfil_2_1 AND regfil_3_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_2_2 AND regfil_3_3 AND regfil_3_4 AND regfil_3_5 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_6 AND regfil_3_7));
</td></tr><tr><td>
FTCPE_regfil_2_3: FTCPE port map (regfil_2_3,regfil_2_3_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_2_3_T <= ((N_PZ_2114 AND holding(3) AND NOT regfil_2_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT holding(3) AND regfil_2_3 AND NOT N_PZ_2155)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1943 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_2_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND regfil_2_3 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2180)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND addrhold(10) AND NOT regfil_2_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT addrhold(10) AND regfil_2_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_3_0 AND regfil_2_0 AND regfil_3_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_2_1 AND regfil_3_2 AND regfil_2_2 AND regfil_3_3 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_4 AND regfil_3_5 AND N_PZ_1941 AND regfil_3_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_3_0 AND regfil_2_0 AND N_PZ_2114 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_1 AND regfil_2_1 AND regfil_3_2 AND regfil_2_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_3 AND NOT holding(3) AND regfil_3_4 AND regfil_3_5 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_2_3 AND regfil_3_6 AND regfil_3_7));
</td></tr><tr><td>
FTCPE_regfil_2_4: FTCPE port map (regfil_2_4,regfil_2_4_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_2_4_T <= ((N_PZ_2114 AND holding(4) AND NOT regfil_2_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT holding(4) AND regfil_2_4 AND NOT N_PZ_2155)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_2181 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_2_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1996 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_2181 AND NOT regfil_2_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND addrhold(11) AND NOT regfil_2_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT addrhold(11) AND regfil_2_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_3_0 AND regfil_2_0 AND regfil_3_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_2_1 AND regfil_3_2 AND regfil_2_2 AND regfil_3_3 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_4 AND regfil_3_5 AND N_PZ_1941 AND regfil_2_3 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_6 AND regfil_3_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_3_0 AND regfil_2_0 AND N_PZ_2114 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_1 AND regfil_2_1 AND regfil_3_2 AND regfil_2_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_3 AND regfil_3_4 AND NOT holding(4) AND regfil_3_5 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_2_3 AND regfil_3_6 AND regfil_2_4 AND regfil_3_7));
</td></tr><tr><td>
FTCPE_regfil_2_5: FTCPE port map (regfil_2_5,regfil_2_5_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_2_5_T <= ((N_PZ_2114 AND holding(5) AND NOT regfil_2_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1941 AND regfil_2_5 AND NOT _mux0014(13)8)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT holding(5) AND regfil_2_5 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _mux0014(13)8)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1265 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_2_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND addrhold(12) AND NOT regfil_2_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT addrhold(12) AND regfil_2_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_2_5 AND _mux0014(13)8)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT alures(5) AND regfil_2_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(5).PIN AND NOT regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regd(0) AND regfil_2_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND NOT regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND NOT regd(0) AND NOT N_PZ_1373 AND _COND_18(5) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_2_5 AND NOT _mux0014(13)8));
</td></tr><tr><td>
FTCPE_regfil_2_6: FTCPE port map (regfil_2_6,regfil_2_6_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_2_6_T <= ((N_PZ_2114 AND NOT regfil_2_6 AND holding(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1941 AND regfil_2_5 AND NOT _mux0014(13)8)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT _mux0014(13)8 AND regfil_2_6 AND NOT N_PZ_2155 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT holding(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND NOT regfil_2_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1888)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND regfil_2_5 AND NOT _mux0014(13)8 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_2_6 AND NOT holding(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND addrhold(13) AND NOT regfil_2_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT addrhold(13) AND regfil_2_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_2_6 AND NOT alures(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(6).PIN AND NOT regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regd(0) AND NOT regfil_2_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(6).PIN AND NOT regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regd(0) AND regfil_2_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND NOT regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND NOT regd(0) AND NOT N_PZ_1373 AND NOT _mux0014(13)8 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_2_6 AND _COND_18(6)));
</td></tr><tr><td>
FTCPE_regfil_2_7: FTCPE port map (regfil_2_7,regfil_2_7_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_2_7_T <= ((N_PZ_2114 AND holding(7) AND NOT regfil_2_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT holding(7) AND NOT _mux0014(13)8 AND regfil_2_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_2155)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1941 AND regfil_2_5 AND NOT _mux0014(13)8 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_2_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1266 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_2_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT holding(7) AND regfil_2_5 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _mux0014(13)8 AND regfil_2_7 AND regfil_2_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND addrhold(14) AND NOT regfil_2_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT addrhold(14) AND regfil_2_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT alures(7) AND regfil_2_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(7).PIN AND NOT regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regd(0) AND regfil_2_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND NOT regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND NOT regd(0) AND _COND_18(7) AND NOT N_PZ_1373 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _mux0014(13)8 AND regfil_2_7));
</td></tr><tr><td>
FTCPE_regfil_3_0: FTCPE port map (regfil_3_0,regfil_3_0_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_3_0_T <= ((N_PZ_1941)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_3_0 AND NOT holding(0) AND N_PZ_2114)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_3_0 AND holding(0) AND N_PZ_2114)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND regfil_3_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1268)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND NOT regfil_3_0 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1268 AND N_PZ_1996)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND addrhold(0) AND NOT regfil_3_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT addrhold(0) AND regfil_3_0));
</td></tr><tr><td>
FTCPE_regfil_3_1: FTCPE port map (regfil_3_1,regfil_3_1_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_3_1_T <= ((regfil_3_0 AND N_PZ_1941)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (holding(1) AND N_PZ_2114 AND NOT regfil_3_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT holding(1) AND N_PZ_2114 AND regfil_3_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND regfil_3_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1946)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND NOT regfil_3_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1262)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND regfil_3_1 AND NOT addrhold(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT regfil_3_1 AND addrhold(1)));
</td></tr><tr><td>
FTCPE_regfil_3_2: FTCPE port map (regfil_3_2,regfil_3_2_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_3_2_T <= ((regfil_3_0 AND regfil_3_1 AND N_PZ_1941)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (holding(2) AND N_PZ_2114 AND NOT regfil_3_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT holding(2) AND N_PZ_2114 AND regfil_3_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND regfil_3_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1945)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND NOT regfil_3_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1944)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND regfil_3_2 AND NOT addrhold(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT regfil_3_2 AND addrhold(2)));
</td></tr><tr><td>
FTCPE_regfil_3_3: FTCPE port map (regfil_3_3,regfil_3_3_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_3_3_T <= ((N_PZ_2114 AND regfil_3_3 AND NOT holding(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT regfil_3_3 AND holding(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_3_0 AND regfil_3_1 AND regfil_3_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1941)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND N_PZ_1943 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_3_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND regfil_3_3 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2180)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND addrhold(3) AND NOT regfil_3_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT addrhold(3) AND regfil_3_3));
</td></tr><tr><td>
FTCPE_regfil_3_4: FTCPE port map (regfil_3_4,regfil_3_4_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_3_4_T <= ((N_PZ_2114 AND regfil_3_4 AND NOT holding(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT regfil_3_4 AND holding(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND regfil_3_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2181)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_3_0 AND regfil_3_1 AND regfil_3_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_3 AND N_PZ_1941)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND N_PZ_1996 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_3_4 AND NOT N_PZ_2181)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND addrhold(4) AND NOT regfil_3_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT addrhold(4) AND regfil_3_4));
</td></tr><tr><td>
FTCPE_regfil_3_5: FTCPE port map (regfil_3_5,regfil_3_5_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_3_5_T <= ((N_PZ_2114 AND regfil_3_5 AND NOT holding(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT regfil_3_5 AND holding(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND regfil_3_5 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2000)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND NOT regfil_3_5 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1265)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_3_0 AND regfil_3_1 AND regfil_3_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_3 AND regfil_3_4 AND N_PZ_1941)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND addrhold(5) AND NOT regfil_3_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT addrhold(5) AND regfil_3_5));
</td></tr><tr><td>
FTCPE_regfil_3_6: FTCPE port map (regfil_3_6,regfil_3_6_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_3_6_T <= ((N_PZ_2114 AND regfil_3_6 AND NOT holding(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT regfil_3_6 AND holding(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND regfil_3_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2106)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND NOT regfil_3_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1888)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_3_0 AND regfil_3_1 AND regfil_3_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_3 AND regfil_3_4 AND regfil_3_5 AND N_PZ_1941)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND regfil_3_6 AND NOT addrhold(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT regfil_3_6 AND addrhold(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(6).PIN AND NOT regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND NOT regfil_3_6));
</td></tr><tr><td>
FTCPE_regfil_3_7: FTCPE port map (regfil_3_7,regfil_3_7_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_3_7_T <= ((N_PZ_2114 AND holding(7) AND NOT regfil_3_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT holding(7) AND regfil_3_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND N_PZ_1266 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_3_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regd(2) AND regd(1) AND regd(0) AND regfil_3_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2001)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND addrhold(7) AND NOT regfil_3_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND state(0) AND NOT addrhold(7) AND regfil_3_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_3_0 AND regfil_3_1 AND regfil_3_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_3 AND regfil_3_4 AND regfil_3_5 AND N_PZ_1941 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_3_6));
</td></tr><tr><td>
FTCPE_regfil_4_0: FTCPE port map (regfil_4_0,regfil_4_0_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_4_0_T <= ((data(0).PIN AND NOT regfil_4_0 AND N_PZ_1061)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(0).PIN AND regfil_4_0 AND N_PZ_1061)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_4_0 AND N_PZ_1100 AND NOT _mux0010(8)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_4_0 AND regfil_2_0 AND N_PZ_2114)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_4_0 AND NOT regfil_2_0 AND N_PZ_2114 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _mux0010(8)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND addrhold(7) AND NOT regfil_4_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT addrhold(7) AND regfil_4_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_4_0 AND _mux0010(8)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_4_0 AND NOT alures(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_0 AND alures(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND NOT regfil_4_0 AND NOT _COND_18(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1373)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND regfil_4_0 AND _COND_18(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1373 AND NOT _mux0010(8)71));
</td></tr><tr><td>
FTCPE_regfil_4_1: FTCPE port map (regfil_4_1,regfil_4_1_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_4_1_T <= ((data(1).PIN AND NOT regfil_4_1 AND N_PZ_1061)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(1).PIN AND regfil_4_1 AND N_PZ_1061)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_4_1 AND N_PZ_1100 AND NOT _mux0010(9)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_4_1 AND N_PZ_2114 AND regfil_2_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_4_1 AND N_PZ_2114 AND NOT regfil_2_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _mux0010(9)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND regfil_4_1 AND NOT addrhold(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT regfil_4_1 AND addrhold(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_4_1 AND _mux0010(9)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_4_1 AND NOT alures(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_1 AND alures(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND NOT regfil_4_1 AND NOT N_PZ_1373 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _COND_18(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND regfil_4_1 AND NOT N_PZ_1373 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	_COND_18(1) AND NOT _mux0010(9)71));
</td></tr><tr><td>
FTCPE_regfil_4_2: FTCPE port map (regfil_4_2,regfil_4_2_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_4_2_T <= ((data(2).PIN AND NOT regfil_4_2 AND N_PZ_1061)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND regfil_4_2 AND N_PZ_1061)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_4_2 AND N_PZ_1100 AND NOT _mux0010(10)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_4_2 AND N_PZ_2114 AND regfil_2_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_4_2 AND N_PZ_2114 AND NOT regfil_2_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _mux0010(10)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND regfil_4_2 AND NOT addrhold(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT regfil_4_2 AND addrhold(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_4_2 AND _mux0010(10)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_4_2 AND NOT alures(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_2 AND alures(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND NOT regfil_4_2 AND NOT N_PZ_1373 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _COND_18(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND regfil_4_2 AND NOT N_PZ_1373 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	_COND_18(2) AND NOT _mux0010(10)71));
</td></tr><tr><td>
FTCPE_regfil_4_3: FTCPE port map (regfil_4_3,regfil_4_3_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_4_3_T <= ((data(3).PIN AND NOT regfil_4_3 AND N_PZ_1061)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(3).PIN AND regfil_4_3 AND N_PZ_1061)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT regfil_4_3 AND regfil_2_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_4_3 AND N_PZ_1100 AND NOT _mux0010(11)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND regfil_4_3 AND NOT regfil_2_3 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _mux0010(11)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1157 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND regfil_4_3 AND NOT addrhold(10))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT regfil_4_3 AND addrhold(10))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_4_3 AND _mux0010(11)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT alures(3) AND regfil_4_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND NOT N_PZ_1373 AND regfil_4_3 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	_COND_18(3) AND NOT _mux0010(11)71));
</td></tr><tr><td>
FTCPE_regfil_4_4: FTCPE port map (regfil_4_4,regfil_4_4_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_4_4_T <= ((data(4).PIN AND NOT regfil_4_4 AND N_PZ_1061)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND regfil_4_4 AND N_PZ_1061)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT regfil_4_4 AND regfil_2_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_4_4 AND N_PZ_1100 AND NOT _mux0010(12)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND regfil_4_4 AND NOT regfil_2_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _mux0010(12)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND regfil_4_4 AND NOT addrhold(11))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT regfil_4_4 AND addrhold(11))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_4_4 AND _mux0010(12)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_4_4 AND NOT alures(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_4 AND alures(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND NOT N_PZ_1373 AND NOT regfil_4_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _COND_18(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND NOT N_PZ_1373 AND regfil_4_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	_COND_18(4) AND NOT _mux0010(12)71));
</td></tr><tr><td>
FTCPE_regfil_4_5: FTCPE port map (regfil_4_5,regfil_4_5_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_4_5_T <= ((data(5).PIN AND NOT regfil_4_5 AND N_PZ_1061)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(5).PIN AND regfil_4_5 AND N_PZ_1061)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT regfil_4_5 AND regfil_2_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_4_5 AND N_PZ_1100 AND NOT _mux0010(13)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND regfil_4_5 AND NOT regfil_2_5 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _mux0010(13)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND regfil_4_5 AND NOT addrhold(12))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT regfil_4_5 AND addrhold(12))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_4_5 AND _mux0010(13)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_4_5 AND NOT alures(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_5 AND alures(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND NOT N_PZ_1373 AND NOT regfil_4_5 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _COND_18(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND NOT N_PZ_1373 AND regfil_4_5 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	_COND_18(5) AND NOT _mux0010(13)71));
</td></tr><tr><td>
FTCPE_regfil_4_6: FTCPE port map (regfil_4_6,regfil_4_6_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_4_6_T <= ((data(6).PIN AND NOT regfil_4_6 AND N_PZ_1061)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(6).PIN AND regfil_4_6 AND N_PZ_1061)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT regfil_4_6 AND regfil_2_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_4_6 AND N_PZ_1100 AND NOT _mux0010(14)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND regfil_4_6 AND NOT regfil_2_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _mux0010(14)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND NOT regd(1) AND NOT regd(0) AND NOT regfil_4_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1888)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND regfil_4_6 AND NOT addrhold(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT regfil_4_6 AND addrhold(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_4_6 AND _mux0010(14)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_4_6 AND NOT alures(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND NOT N_PZ_1373 AND regfil_4_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	_COND_18(6) AND NOT _mux0010(14)71));
</td></tr><tr><td>
FTCPE_regfil_4_7: FTCPE port map (regfil_4_7,regfil_4_7_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_4_7_T <= ((data(7).PIN AND NOT regfil_4_7 AND N_PZ_1061)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(7).PIN AND regfil_4_7 AND N_PZ_1061)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT regfil_4_7 AND regfil_2_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_4_7 AND N_PZ_1100 AND NOT _mux0010(15)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND regfil_4_7 AND NOT regfil_2_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _mux0010(15)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND regfil_4_7 AND NOT addrhold(14))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT regfil_4_7 AND addrhold(14))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_4_7 AND _mux0010(15)71)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_4_7 AND NOT alures(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_7 AND alures(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND NOT _COND_18(7) AND NOT N_PZ_1373 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_4_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND _COND_18(7) AND NOT N_PZ_1373 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_4_7 AND NOT _mux0010(15)71));
</td></tr><tr><td>
FTCPE_regfil_5_0: FTCPE port map (regfil_5_0,regfil_5_0_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_5_0_T <= ((N_PZ_1528)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_3_0 AND N_PZ_1533)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_1_0 AND N_PZ_1432)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (sp(0) AND N_PZ_1536)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(0).PIN AND NOT regfil_5_0 AND N_PZ_1062)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(0).PIN AND regfil_5_0 AND N_PZ_1062)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_0 AND NOT regfil_3_0 AND N_PZ_2114)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_0 AND _COND_18(0) AND N_PZ_2196)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_0 AND regfil_3_0 AND N_PZ_2114)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_0 AND NOT _COND_18(0) AND N_PZ_2196)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND addrhold(0) AND NOT regfil_5_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT addrhold(0) AND regfil_5_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regfil_5_0 AND NOT alures(0) AND N_PZ_1129)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT regfil_5_0 AND alures(0) AND N_PZ_1129)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_5_0));
</td></tr><tr><td>
FTCPE_regfil_5_1: FTCPE port map (regfil_5_1,regfil_5_1_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_5_1_T <= ((regfil_5_0 AND N_PZ_1528)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (data(1).PIN AND NOT regfil_5_1 AND N_PZ_1062)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(1).PIN AND regfil_5_1 AND N_PZ_1062)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_0 AND NOT regfil_5_1 AND N_PZ_1580)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_0 AND regfil_3_1 AND N_PZ_1533)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_0 AND regfil_5_1 AND N_PZ_1580)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_0 AND sp(1) AND N_PZ_1536)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_0 AND regfil_1_1 AND N_PZ_1432)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_3_0 AND regfil_3_1 AND N_PZ_1533)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_1_0 AND regfil_1_1 AND N_PZ_1432)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND regfil_3_1 AND NOT regfil_5_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT regfil_3_1 AND regfil_5_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_1 AND _COND_18(1) AND N_PZ_2196)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_1 AND N_PZ_1129 AND N_PZ_1262)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT sp(0) AND sp(1) AND N_PZ_1536)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_0 AND regfil_3_0 AND NOT regfil_3_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1533)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_0 AND regfil_1_0 AND NOT regfil_1_1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1432)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_0 AND sp(0) AND NOT sp(1) AND N_PZ_1536)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND addrhold(1) AND NOT regfil_5_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT addrhold(1) AND regfil_5_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regfil_5_1 AND N_PZ_1129 AND NOT alures(1)));
</td></tr><tr><td>
FTCPE_regfil_5_2: FTCPE port map (regfil_5_2,regfil_5_2_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_5_2_T <= ((data(2).PIN AND N_PZ_1062 AND NOT regfil_5_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(2).PIN AND N_PZ_1062 AND regfil_5_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND regfil_3_2 AND NOT regfil_5_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_2 AND NOT _mux0009(2)72 AND N_PZ_1100)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT regfil_3_2 AND regfil_5_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _mux0009(2)72)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_2 AND NOT _mux0009(2)72 AND _COND_18(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2196)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND addrhold(2) AND NOT regfil_5_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT addrhold(2) AND regfil_5_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_5_2 AND _mux0009(2)72)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND N_PZ_1129 AND regfil_5_2 AND NOT alures(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND N_PZ_1129 AND NOT regfil_5_2 AND alures(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT N_PZ_1373 AND N_PZ_1129 AND NOT regfil_5_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _COND_18(2)));
</td></tr><tr><td>
FTCPE_regfil_5_3: FTCPE port map (regfil_5_3,regfil_5_3_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_5_3_T <= ((data(3).PIN AND NOT regfil_5_3 AND N_PZ_1062)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(3).PIN AND regfil_5_3 AND N_PZ_1062)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_3 AND N_PZ_2114 AND NOT regfil_3_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_3 AND NOT regfil_5_2 AND N_PZ_1580)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_3 AND _COND_18(3) AND N_PZ_2196)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_3 AND N_PZ_2114 AND regfil_3_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_3 AND N_PZ_1129 AND N_PZ_1157)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_3 AND regfil_5_2 AND N_PZ_1580)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_1_3 AND N_PZ_2004 AND N_PZ_1432)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_3_3 AND NOT N_PZ_2358 AND N_PZ_1533)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_3_3 AND N_PZ_2358 AND N_PZ_1533)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (sp(3) AND NOT Madd__AUX_11__or0001 AND N_PZ_1536)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT sp(3) AND Madd__AUX_11__or0001 AND N_PZ_1536)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_0 AND regfil_5_1 AND regfil_5_2 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1528)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_2 AND regfil_1_2 AND NOT regfil_1_3 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1432)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_2 AND NOT regfil_1_3 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__addsub0000__or0000 AND N_PZ_1432)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_1_2 AND NOT regfil_1_3 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	Madd__addsub0000__or0000 AND N_PZ_1432)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND regfil_5_3 AND NOT addrhold(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT regfil_5_3 AND addrhold(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regfil_5_3 AND N_PZ_1129 AND NOT alures(3)));
</td></tr><tr><td>
FTCPE_regfil_5_4: FTCPE port map (regfil_5_4,regfil_5_4_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_5_4_T <= ((data(4).PIN AND N_PZ_1062 AND NOT regfil_5_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(4).PIN AND N_PZ_1062 AND regfil_5_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT regfil_5_4 AND regfil_3_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_4 AND NOT _mux0009(4)72 AND N_PZ_1100)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_4 AND NOT _COND_18(4) AND N_PZ_2196)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND regfil_5_4 AND NOT _mux0009(4)72 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_3_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_4 AND NOT _mux0009(4)72 AND _COND_18(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2196)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND addrhold(4) AND NOT regfil_5_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT addrhold(4) AND regfil_5_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_5_4 AND _mux0009(4)72)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND N_PZ_1129 AND regfil_5_4 AND NOT alures(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND N_PZ_1129 AND NOT regfil_5_4 AND alures(4)));
</td></tr><tr><td>
FTCPE_regfil_5_5: FTCPE port map (regfil_5_5,regfil_5_5_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_5_5_T <= ((data(5).PIN AND N_PZ_1062 AND NOT regfil_5_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(5).PIN AND N_PZ_1062 AND regfil_5_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT regfil_5_5 AND regfil_3_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_5 AND NOT _mux0009(5)72 AND N_PZ_1100)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_5 AND NOT _COND_18(5) AND N_PZ_2196)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND regfil_5_5 AND NOT _mux0009(5)72 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_3_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_5 AND NOT _mux0009(5)72 AND _COND_18(5) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2196)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND addrhold(5) AND NOT regfil_5_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT addrhold(5) AND regfil_5_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_5_5 AND _mux0009(5)72)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND N_PZ_1129 AND regfil_5_5 AND NOT alures(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND N_PZ_1129 AND NOT regfil_5_5 AND alures(5)));
</td></tr><tr><td>
FTCPE_regfil_5_6: FTCPE port map (regfil_5_6,regfil_5_6_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_5_6_T <= ((data(6).PIN AND N_PZ_1062 AND NOT regfil_5_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(6).PIN AND N_PZ_1062 AND regfil_5_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND regfil_3_6 AND NOT regfil_5_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1129 AND NOT regfil_5_6 AND N_PZ_1888)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_6 AND NOT _mux0009(6)72 AND N_PZ_1100)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_2114 AND NOT regfil_3_6 AND regfil_5_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _mux0009(6)72)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_6 AND NOT _mux0009(6)72 AND _COND_18(6) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_2196)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND addrhold(6) AND NOT regfil_5_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT addrhold(6) AND regfil_5_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_5_6 AND _mux0009(6)72)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND N_PZ_1129 AND regfil_5_6 AND NOT alures(6)));
</td></tr><tr><td>
FTCPE_regfil_5_7: FTCPE port map (regfil_5_7,regfil_5_7_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_5_7_T <= ((data(7).PIN AND NOT regfil_5_7 AND N_PZ_1062)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT data(7).PIN AND regfil_5_7 AND N_PZ_1062)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT _COND_18(7) AND NOT regfil_5_7 AND N_PZ_2196)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_7 AND N_PZ_1100 AND NOT _mux0009(7)72)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_5_7 AND N_PZ_2114 AND regfil_3_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (_COND_18(7) AND regfil_5_7 AND N_PZ_2196 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _mux0009(7)72)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regfil_5_7 AND N_PZ_2114 AND NOT regfil_3_7 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _mux0009(7)72)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND regfil_5_7 AND NOT addrhold(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND NOT state(0) AND NOT regfil_5_7 AND addrhold(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT regfil_5_7 AND _mux0009(7)72)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regfil_5_7 AND N_PZ_1129 AND NOT alures(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT regfil_5_7 AND N_PZ_1129 AND alures(7)));
</td></tr><tr><td>
FDCPE_regfil_6_0: FDCPE port map (regfil_6_0,regfil_6_0_D,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_6_0_D <= ((NOT N_PZ_2186 AND regfil_6_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1268 AND N_PZ_1996 AND regfil_6_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND NOT regd(0) AND NOT N_PZ_1268 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1996 AND NOT regfil_6_0));
</td></tr><tr><td>
FTCPE_regfil_6_1: FTCPE port map (regfil_6_1,regfil_6_1_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_6_1_T <= ((NOT N_PZ_1262 AND N_PZ_2186 AND regfil_6_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1262 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_6_1));
</td></tr><tr><td>
FTCPE_regfil_6_2: FTCPE port map (regfil_6_2,regfil_6_2_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_6_2_T <= ((regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1945 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_6_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	alures(2) AND NOT regfil_6_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(2).PIN AND regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regd(0) AND NOT regfil_6_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND NOT regd(0) AND NOT N_PZ_1373 AND NOT _COND_18(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_6_2));
</td></tr><tr><td>
FTCPE_regfil_6_3: FTCPE port map (regfil_6_3,regfil_6_3_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_6_3_T <= ((regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1943 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_6_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(2) AND NOT state(4) AND NOT state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND NOT N_PZ_1943 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_6_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND NOT N_PZ_1373 AND NOT N_PZ_1943 AND regfil_6_3 AND N_PZ_1921));
</td></tr><tr><td>
FDCPE_regfil_6_4: FDCPE port map (regfil_6_4,regfil_6_4_D,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_6_4_D <= ((NOT N_PZ_2186 AND regfil_6_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_PZ_1996 AND NOT N_PZ_2181 AND regfil_6_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1996 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_2181 AND NOT regfil_6_4));
</td></tr><tr><td>
FTCPE_regfil_6_5: FTCPE port map (regfil_6_5,regfil_6_5_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_6_5_T <= ((NOT N_PZ_1265 AND regfil_6_5 AND N_PZ_2186)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1265 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_6_5));
</td></tr><tr><td>
FTCPE_regfil_6_6: FTCPE port map (regfil_6_6,regfil_6_6_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_6_6_T <= ((regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1888 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_6_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_2106 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_6_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(6).PIN AND regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regd(0) AND NOT regfil_6_6));
</td></tr><tr><td>
FTCPE_regfil_6_7: FTCPE port map (regfil_6_7,regfil_6_7_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_6_7_T <= ((NOT N_PZ_1266 AND N_PZ_2186 AND regfil_6_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1266 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_6_7));
</td></tr><tr><td>
FTCPE_regfil_7_0: FTCPE port map (regfil_7_0,regfil_7_0_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_7_0_T <= ((regfil_7_0 AND NOT alures(0) AND N_PZ_1060)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_7_0 AND alures(0) AND N_PZ_1060)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(0).PIN AND regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND NOT regfil_7_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(0).PIN AND regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND regfil_7_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	holding(0) AND NOT regfil_7_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT holding(0) AND regfil_7_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_7_0 AND NOT regfil_7_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_7_0 AND regfil_7_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND regd(0) AND regfil_7_0 AND _COND_18(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1373)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT regfil_7_0 AND NOT _COND_18(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1373)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT data(5).PIN AND carry AND NOT regfil_7_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT data(5).PIN AND NOT carry AND regfil_7_0)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT data(5).PIN AND regfil_7_0 AND NOT regfil_7_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT data(5).PIN AND NOT regfil_7_0 AND regfil_7_7));
</td></tr><tr><td>
FTCPE_regfil_7_1: FTCPE port map (regfil_7_1,regfil_7_1_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_7_1_T <= ((regfil_7_1 AND NOT alures(1) AND N_PZ_1060)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_7_1 AND alures(1) AND N_PZ_1060)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(1).PIN AND regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND NOT regfil_7_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(1).PIN AND regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND regfil_7_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND N_PZ_1890)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_7_1 AND NOT holding(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_7_1 AND holding(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_7_0 AND NOT regfil_7_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_7_0 AND regfil_7_1)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND regd(0) AND regfil_7_1 AND NOT N_PZ_1373 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	_COND_18(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT regfil_7_1 AND NOT N_PZ_1373 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _COND_18(1)));
</td></tr><tr><td>
FTCPE_regfil_7_2: FTCPE port map (regfil_7_2,regfil_7_2_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_7_2_T <= ((regfil_7_2 AND NOT alures(2) AND N_PZ_1060)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_7_2 AND alures(2) AND N_PZ_1060)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(2).PIN AND regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND NOT regfil_7_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(2).PIN AND regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND regfil_7_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND N_PZ_1890)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_7_2 AND NOT holding(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_7_2 AND holding(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_7_3 AND NOT regfil_7_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_7_3 AND regfil_7_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND regd(0) AND regfil_7_2 AND NOT N_PZ_1373 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	_COND_18(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT regfil_7_2 AND NOT N_PZ_1373 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _COND_18(2)));
</td></tr><tr><td>
FTCPE_regfil_7_3: FTCPE port map (regfil_7_3,regfil_7_3_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_7_3_T <= ((regfil_7_3 AND NOT alures(3) AND N_PZ_1060)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_7_3 AND alures(3) AND N_PZ_1060)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(3).PIN AND regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND NOT regfil_7_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(3).PIN AND regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND regfil_7_3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_7_3 AND NOT holding(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_7_3 AND holding(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_7_3 AND NOT regfil_7_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_7_3 AND regfil_7_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_7_3 AND NOT regfil_7_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_7_3 AND regfil_7_2)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND regd(0) AND regfil_7_3 AND NOT N_PZ_1373 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	_COND_18(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT regfil_7_3 AND NOT N_PZ_1373 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _COND_18(3)));
</td></tr><tr><td>
FTCPE_regfil_7_4: FTCPE port map (regfil_7_4,regfil_7_4_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_7_4_T <= ((regfil_7_4 AND NOT alures(4) AND N_PZ_1060)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_7_4 AND alures(4) AND N_PZ_1060)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(4).PIN AND regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND NOT regfil_7_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(4).PIN AND regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND regfil_7_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	holding(4) AND NOT regfil_7_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT holding(4) AND regfil_7_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_7_4 AND NOT regfil_7_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_7_4 AND regfil_7_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_7_3 AND NOT regfil_7_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_7_3 AND regfil_7_4)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT N_PZ_1373 AND regfil_7_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	_COND_18(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT N_PZ_1373 AND NOT regfil_7_4 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _COND_18(4)));
</td></tr><tr><td>
FTCPE_regfil_7_5: FTCPE port map (regfil_7_5,regfil_7_5_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_7_5_T <= ((regfil_7_5 AND NOT alures(5) AND N_PZ_1060)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_7_5 AND alures(5) AND N_PZ_1060)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(5).PIN AND regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND NOT regfil_7_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(5).PIN AND regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND regfil_7_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_7_5 AND NOT holding(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_7_5 AND holding(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_7_5 AND NOT regfil_7_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_7_5 AND regfil_7_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_7_4 AND NOT regfil_7_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_7_4 AND regfil_7_5)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT N_PZ_1373 AND regfil_7_5 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	_COND_18(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT N_PZ_1373 AND NOT regfil_7_5 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _COND_18(5)));
</td></tr><tr><td>
FTCPE_regfil_7_6: FTCPE port map (regfil_7_6,regfil_7_6_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_7_6_T <= ((regfil_7_6 AND NOT alures(6) AND N_PZ_1060)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_7_6 AND alures(6) AND N_PZ_1060)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(6).PIN AND regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND NOT regfil_7_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(6).PIN AND regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND regfil_7_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_7_6 AND NOT holding(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_7_6 AND holding(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_7_6 AND NOT regfil_7_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_7_6 AND regfil_7_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_7_5 AND NOT regfil_7_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_7_5 AND regfil_7_6)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT N_PZ_1373 AND regfil_7_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	_COND_18(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT N_PZ_1373 AND NOT regfil_7_6 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _COND_18(6)));
</td></tr><tr><td>
FTCPE_regfil_7_7: FTCPE port map (regfil_7_7,regfil_7_7_T,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regfil_7_7_T <= ((regfil_7_7 AND NOT alures(7) AND N_PZ_1060)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT regfil_7_7 AND alures(7) AND N_PZ_1060)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND data(7).PIN AND regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND NOT regfil_7_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT data(7).PIN AND regd(2) AND regd(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(0) AND regfil_7_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_7_7 AND NOT holding(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_7_7 AND holding(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND regfil_7_0 AND NOT regfil_7_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT regfil_7_0 AND regfil_7_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND regfil_7_6 AND NOT regfil_7_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regfil_7_6 AND regfil_7_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND regd(0) AND _COND_18(7) AND NOT N_PZ_1373 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regfil_7_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT _COND_18(7) AND NOT N_PZ_1373 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regfil_7_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT data(5).PIN AND carry AND NOT regfil_7_7)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT data(5).PIN AND NOT carry AND regfil_7_7));
</td></tr><tr><td>
FTCPE_regs0: FTCPE port map (regs(0),regs_T(0),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regs_T(0) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT regs(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND NOT regs(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND regs(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT _cmp_eq0004 AND regs(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND regs(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1819 AND NOT regs(0)));
</td></tr><tr><td>
FTCPE_regs1: FTCPE port map (regs(1),regs_T(1),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regs_T(1) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(1).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND NOT regs(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(1).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND regs(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(1).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT _cmp_eq0004 AND NOT regs(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(1).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT _cmp_eq0004 AND regs(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regs(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT regs(1)));
</td></tr><tr><td>
FTCPE_regs2: FTCPE port map (regs(2),regs_T(2),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;regs_T(2) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND NOT regs(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(2).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND regs(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(2).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT _cmp_eq0004 AND NOT regs(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(2).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND NOT _cmp_eq0004 AND regs(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND NOT regs(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT regs(2)));
</td></tr><tr><td>
FDCPE_sign: FDCPE port map (sign,sign_D,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sign_D <= ((N_PZ_1894 AND alures(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1894 AND sign));
</td></tr><tr><td>
FTCPE_sp0: FTCPE port map (sp(0),sp_T(0),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sp_T(0) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND addrhold(0) AND NOT sp(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT addrhold(0) AND sp(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND regfil_5_0 AND NOT sp(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND NOT regfil_5_0 AND sp(0)));
</td></tr><tr><td>
FTCPE_sp1: FTCPE port map (sp(1),sp_T(1),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sp_T(1) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND addrhold(1) AND NOT sp(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT addrhold(1) AND sp(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND sp(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND regfil_5_1 AND NOT sp(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND NOT regfil_5_1 AND sp(1)));
</td></tr><tr><td>
FTCPE_sp2: FTCPE port map (sp(2),sp_T(2),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sp_T(2) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND addrhold(2) AND NOT sp(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT addrhold(2) AND sp(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND sp(0) AND sp(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND regfil_5_2 AND NOT sp(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND NOT regfil_5_2 AND sp(2)));
</td></tr><tr><td>
FTCPE_sp3: FTCPE port map (sp(3),sp_T(3),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sp_T(3) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND addrhold(3) AND NOT sp(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT addrhold(3) AND sp(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND regfil_5_3 AND NOT sp(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND NOT regfil_5_3 AND sp(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND sp(2) AND sp(0) AND sp(1)));
</td></tr><tr><td>
FTCPE_sp4: FTCPE port map (sp(4),sp_T(4),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sp_T(4) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND addrhold(4) AND NOT sp(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT addrhold(4) AND sp(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND N_PZ_2168)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(3)));
</td></tr><tr><td>
FTCPE_sp5: FTCPE port map (sp(5),sp_T(5),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sp_T(5) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND addrhold(5) AND NOT sp(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT addrhold(5) AND sp(5))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND NOT N_PZ_1981)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(3) AND sp(4)));
</td></tr><tr><td>
FTCPE_sp6: FTCPE port map (sp(6),sp_T(6),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sp_T(6) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND addrhold(6) AND NOT sp(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT addrhold(6) AND sp(6))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND N_PZ_2169)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(5) AND sp(3) AND sp(4)));
</td></tr><tr><td>
FTCPE_sp7: FTCPE port map (sp(7),sp_T(7),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sp_T(7) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND addrhold(7) AND NOT sp(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT addrhold(7) AND sp(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND NOT N_PZ_1982)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(5) AND sp(3) AND sp(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	sp(6)));
</td></tr><tr><td>
FTCPE_sp8: FTCPE port map (sp(8),sp_T(8),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sp_T(8) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND addrhold(8) AND NOT sp(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT addrhold(8) AND sp(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND regfil_4_0 AND NOT sp(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND NOT regfil_4_0 AND sp(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(5) AND sp(3) AND sp(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	sp(6) AND sp(7)));
</td></tr><tr><td>
FTCPE_sp9: FTCPE port map (sp(9),sp_T(9),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sp_T(9) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND addrhold(9) AND NOT sp(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT addrhold(9) AND sp(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND regfil_4_1 AND NOT sp(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND NOT regfil_4_1 AND sp(9))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(5) AND sp(3) AND sp(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	sp(6) AND sp(7) AND sp(8)));
</td></tr><tr><td>
FTCPE_sp10: FTCPE port map (sp(10),sp_T(10),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sp_T(10) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND addrhold(10) AND NOT sp(10))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT addrhold(10) AND sp(10))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND regfil_4_2 AND NOT sp(10))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND NOT regfil_4_2 AND sp(10))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(5) AND sp(3) AND sp(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	sp(6) AND sp(7) AND sp(8) AND sp(9)));
</td></tr><tr><td>
FTCPE_sp11: FTCPE port map (sp(11),sp_T(11),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sp_T(11) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND addrhold(11) AND NOT sp(11))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT addrhold(11) AND sp(11))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND regfil_4_3 AND NOT sp(11))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND NOT regfil_4_3 AND sp(11))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(5) AND sp(3) AND sp(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	sp(6) AND sp(10) AND sp(7) AND sp(8) AND sp(9)));
</td></tr><tr><td>
FTCPE_sp12: FTCPE port map (sp(12),sp_T(12),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sp_T(12) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND addrhold(12) AND NOT sp(12))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT addrhold(12) AND sp(12))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND NOT N_PZ_1929)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(5) AND sp(3) AND sp(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	sp(6) AND sp(11) AND sp(10) AND sp(7) AND sp(8) AND sp(9)));
</td></tr><tr><td>
FTCPE_sp13: FTCPE port map (sp(13),sp_T(13),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sp_T(13) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND addrhold(13) AND NOT sp(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT addrhold(13) AND sp(13))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND NOT N_PZ_1848)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(5) AND sp(3) AND sp(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	sp(6) AND sp(11) AND sp(10) AND sp(7) AND sp(8) AND sp(9) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	sp(12)));
</td></tr><tr><td>
FTCPE_sp14: FTCPE port map (sp(14),sp_T(14),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sp_T(14) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND addrhold(14) AND NOT sp(14))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT addrhold(14) AND sp(14))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND N_PZ_2105)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(5) AND sp(3) AND sp(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	sp(6) AND sp(11) AND sp(10) AND sp(7) AND sp(8) AND sp(9) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	sp(12) AND sp(13)));
</td></tr><tr><td>
FTCPE_sp15: FTCPE port map (sp(15),sp_T(15),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sp_T(15) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND sp(15) AND NOT addrhold(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND NOT sp(15) AND addrhold(15))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND data(5).PIN AND NOT N_PZ_1849)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(5) AND sp(3) AND sp(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	sp(6) AND sp(11) AND sp(10) AND sp(7) AND sp(8) AND sp(9) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	sp(12) AND sp(13) AND sp(14)));
</td></tr><tr><td>
FTCPE_state0: FTCPE port map (state(0),state_T(0),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;state_T(0) <= ((N_PZ_1065)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (reset AND NOT state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(2) AND state(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (state(3) AND state(1) AND NOT N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(0) AND NOT N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(2) AND NOT state(0) AND NOT N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(1) AND NOT statehold(0) AND N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (state(3) AND state(2) AND state(4) AND NOT N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(0) AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(0) AND NOT data(7).PIN AND N_PZ_1209 AND NOT N_PZ_1921)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(4) AND NOT state(1) AND NOT N_PZ_1209 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	regd(2) AND regd(1) AND NOT regd(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(0) AND data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND data(6).PIN AND data(7).PIN AND N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(0) AND data(1).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND N_PZ_1209 AND N_PZ_1916 AND NOT parity)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(0) AND data(4).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND data(6).PIN AND data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(0).PIN AND data(6).PIN AND data(7).PIN AND data(5).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND data(1).PIN AND data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND N_PZ_1209 AND NOT sign)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND data(1).PIN AND data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND N_PZ_1209 AND sign)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1209 AND N_PZ_1819 AND parity)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND NOT data(5).PIN AND N_PZ_1209 AND NOT carry)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND NOT data(5).PIN AND N_PZ_1209 AND carry)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(0) AND NOT data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND NOT data(5).PIN AND N_PZ_1209 AND NOT zero)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(0) AND NOT data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND NOT data(5).PIN AND N_PZ_1209 AND zero));
</td></tr><tr><td>
FDCPE_state1: FDCPE port map (state(1),state_D(1),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;state_D(1) <= ((state(1) AND N_PZ_1066)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(1) AND N_PZ_1209 AND statehold(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (state(3) AND state(2) AND NOT state(4) AND NOT state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND NOT data(3).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND data(2).PIN AND NOT data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND NOT data(1).PIN AND NOT data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (state(3) AND state(2) AND state(4) AND NOT state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0) AND NOT N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND NOT data(2).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND NOT data(5).PIN AND N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND NOT data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND data(0).PIN AND data(7).PIN AND N_PZ_1209)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND data(3).PIN AND NOT data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND N_PZ_1209 AND N_PZ_1819 AND parity)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(7).PIN AND N_PZ_1209 AND N_PZ_1819 AND NOT parity)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(4) AND NOT state(1) AND state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1209 AND regd(2) AND regd(1) AND NOT regd(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND data(7).PIN AND data(5).PIN AND N_PZ_1209 AND sign)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND data(7).PIN AND NOT data(5).PIN AND N_PZ_1209 AND carry)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND data(7).PIN AND data(5).PIN AND N_PZ_1209 AND NOT sign)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND data(7).PIN AND NOT data(5).PIN AND N_PZ_1209 AND NOT carry)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND NOT data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND data(7).PIN AND NOT data(5).PIN AND N_PZ_1209 AND zero)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND NOT data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND data(7).PIN AND NOT data(5).PIN AND N_PZ_1209 AND NOT zero)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1209 AND regd(2) AND regd(1) AND NOT regd(0) AND NOT N_PZ_1373)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND N_PZ_1209));
</td></tr><tr><td>
FDCPE_state2: FDCPE port map (state(2),state_D(2),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;state_D(2) <= ((NOT reset AND state(2) AND state(1) AND NOT state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND NOT state(2) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND state(0) AND statehold(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(1) AND regd(2) AND regd(1) AND NOT regd(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND data(1).PIN AND data(6).PIN AND N_PZ_1966)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND NOT _cmp_eq0004 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1921));
</td></tr><tr><td>
FTCPE_state3: FTCPE port map (state(3),state_T(3),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;state_T(3) <= ((N_PZ_1894)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (reset AND state(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(2) AND state(1) AND state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (state(3) AND NOT state(2) AND NOT state(1) AND state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(2) AND NOT state(1) AND state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT N_PZ_1065 AND statehold(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND data(1).PIN AND N_PZ_1966)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(2) AND NOT state(4) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT data(6).PIN AND data(7).PIN));
</td></tr><tr><td>
FTCPE_state4: FTCPE port map (state(4),state_T(4),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;state_T(4) <= ((reset AND state(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND state(2) AND state(4) AND NOT state(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(3) AND NOT state(2) AND state(4) AND state(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND state(3) AND state(2) AND state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (state(3) AND NOT state(2) AND state(4) AND NOT state(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(2) AND state(4) AND NOT state(1) AND state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT statehold(4)));
</td></tr><tr><td>
FTCPE_statehold0: FTCPE port map (statehold(0),statehold_T(0),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;statehold_T(0) <= ((statehold(0) AND N_PZ_2232)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND statehold(0) AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND statehold(0) AND NOT data(4).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT statehold(0) AND data(4).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(6).PIN AND NOT data(7).PIN));
</td></tr><tr><td>
FTCPE_statehold1: FTCPE port map (statehold(1),statehold_T(1),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;statehold_T(1) <= ((N_PZ_2232 AND NOT statehold(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT statehold(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND NOT statehold(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND statehold(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND NOT statehold(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(7).PIN AND data(5).PIN AND statehold(1)));
</td></tr><tr><td>
FTCPE_statehold2: FTCPE port map (statehold(2),statehold_T(2),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;statehold_T(2) <= ((N_PZ_2232 AND statehold(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND NOT statehold(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND NOT statehold(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND statehold(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND NOT statehold(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(5).PIN AND statehold(2)));
</td></tr><tr><td>
FTCPE_statehold3: FTCPE port map (statehold(3),statehold_T(3),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;statehold_T(3) <= ((N_PZ_2232 AND statehold(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	statehold(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND statehold(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND statehold(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	N_PZ_1819 AND NOT statehold(3)));
</td></tr><tr><td>
FTCPE_statehold4: FTCPE port map (statehold(4),statehold_T(4),clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;statehold_T(4) <= ((N_PZ_2232 AND statehold(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT statehold(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND NOT data(2).PIN AND data(1).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT statehold(4))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	data(5).PIN AND statehold(4)));
</td></tr><tr><td>
FDCPE_zero: FDCPE port map (zero,zero_D,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;zero_D <= ((N_PZ_1894 AND aluzout)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT N_PZ_1894 AND zero));
</td></tr><tr><td>
</td></tr><tr><td>
Register Legend:
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FDCPE (Q,D,C,CLR,PRE,CE); 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FDDCPE (Q,D,C,CLR,PRE,CE); 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FTCPE (Q,D,C,CLR,PRE,CE); 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FTDCPE (Q,D,C,CLR,PRE,CE); 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LDCP  (Q,D,G,CLR,PRE); 
</td></tr><tr><td>
</td></tr>
</table>
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