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<body class="pgBgnd">
<span id="legend" class="pgRef"><h3 align="center">Legends</h3>
<table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td align="right"><form><input type="button" onclick="javascript:document.location.href='logiclegend.htm'" value="brief"></form></td></tr></table>
<table align="center" width="90%" border="1" cellpadding="0" cellspacing="0">
<tr>
<th width="20%">Acronym</th>
<th width="80%">Verbose Description</th>
</tr>
<tr>
<td width="20%"> *</td>
<td width="80%"> User Assigned</td>
</tr>
<tr>
<td width="20%"> (b)</td>
<td width="80%"> Buried macrocell</td>
</tr>
<tr>
<td width="20%"> CTC</td>
<td width="80%"> Control Term Clock</td>
</tr>
<tr>
<td width="20%"> CTR</td>
<td width="80%"> Control Term Reset</td>
</tr>
<tr>
<td width="20%"> CTS</td>
<td width="80%"> Control Term Set</td>
</tr>
<tr>
<td width="20%"> CTE</td>
<td width="80%"> Control Term Output Enable</td>
</tr>
<tr>
<td width="20%"> DFF</td>
<td width="80%"> D Flip-Flop</td>
</tr>
<tr>
<td width="20%"> DDFF</td>
<td width="80%"> Dual-edge triggered D Flip-Flop</td>
</tr>
<tr>
<td width="20%"> DEFF</td>
<td width="80%"> D Flip-Flop with Enable</td>
</tr>
<tr>
<td width="20%"> DDEFF</td>
<td width="80%"> Dual-edge triggered D Flip-Flop with Enable</td>
</tr>
<tr>
<td width="20%"> DG</td>
<td width="80%"> DataGATE</td>
</tr>
<tr>
<td width="20%"> DGE</td>
<td width="80%"> DataGATE Enable</td>
</tr>
<tr>
<td width="20%"> FB#</td>
<td width="80%"> Function Block number</td>
</tr>
<tr>
<td width="20%"> GCK#</td>
<td width="80%"> Global Clock number</td>
</tr>
<tr>
<td width="20%"> GTS#</td>
<td width="80%"> Global Output Enable number</td>
</tr>
<tr>
<td width="20%"> GSR</td>
<td width="80%"> Global Set/Reset</td>
</tr>
<tr>
<td width="20%"> I</td>
<td width="80%"> Input</td>
</tr>
<tr>
<td width="20%"> I/O</td>
<td width="80%"> Input/Output</td>
</tr>
<tr>
<td width="20%"> IR</td>
<td width="80%"> Direct Input Register</td>
</tr>
<tr>
<td width="20%"> KPR</td>
<td width="80%"> Unused I/O with weak keeper (leave unconnected)</td>
</tr>
<tr>
<td width="20%"> Latch</td>
<td width="80%"> Transparent latch</td>
</tr>
<tr>
<td width="20%"> MC#</td>
<td width="80%"> Macrocell number</td>
</tr>
<tr>
<td width="20%"> O</td>
<td width="80%"> Output</td>
</tr>
<tr>
<td width="20%"> OD</td>
<td width="80%"> Open Drain</td>
</tr>
<tr>
<td width="20%"> PU</td>
<td width="80%"> Pullup</td>
</tr>
<tr>
<td width="20%"> /S</td>
<td width="80%"> After any flop/latch type indicates initial state is Set</td>
</tr>
<tr>
<td width="20%"> TCK</td>
<td width="80%"> One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. Test operations of the device are synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pull-up forces TCK to a high level if left unconnected.</td>
</tr>
<tr>
<td width="20%"> TDI</td>
<td width="80%"> One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial input for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level if left unconnected.</td>
</tr>
<tr>
<td width="20%"> TDO</td>
<td width="80%"> One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial output for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level when it is not driven from an external source.</td>
</tr>
<tr>
<td width="20%"> TFF</td>
<td width="80%"> Toggle Flip-Flop</td>
</tr>
<tr>
<td width="20%"> TDFF</td>
<td width="80%"> Dual edge triggered Toggle Flip-Flop</td>
</tr>
<tr>
<td width="20%"> TMS</td>
<td width="80%"> One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It directs the device through its Test Access Port controller states. An internal pull-up forces TDI to a high level when it is not driven from an external source. TMS also provides the optional test reset signal of IEEE Std 1149 or IEEE Std 1532. </td>
</tr>
<tr>
<td width="20%"> VREF</td>
<td width="80%"> Pin used to compare to an external voltage reference for high speed I/O Standards.</td>
</tr>
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