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[/] [cpu8080/] [trunk/] [project/] [cpu8080_html/] [fit/] [pinlegendV.htm] - Rev 33
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<span id="legend" class="pgRef"><h3 align="center">Legends</h3>
<table align="center" width="90%" border="0" cellpadding="0" cellspacing="0"><tr><td align="right"><form><input type="button" onclick="javascript:document.location.href='pinlegend.htm'" value="brief"></form></td></tr></table>
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<th width="20%">Acronym</th>
<th width="80%">Verbose Description</th>
</tr>
<tr>
<td width="20%"> CLK</td>
<td width="80%"> Global Clock</td>
</tr>
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<td width="20%"> DG</td>
<td width="80%"> DataGATE</td>
</tr>
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<td width="20%"> DGE</td>
<td width="80%"> DataGATE Enable</td>
</tr>
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<td width="20%"> GCK0</td>
<td width="80%"> Global clock zero</td>
</tr>
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<td width="20%"> GCK1</td>
<td width="80%"> Global clock one</td>
</tr>
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<td width="20%"> GCK2</td>
<td width="80%"> Global clock two</td>
</tr>
<tr>
<td width="20%"> GND</td>
<td width="80%"> Dedicated Ground Pin</td>
</tr>
<tr>
<td width="20%"> GSR</td>
<td width="80%"> Global set-reset</td>
</tr>
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<td width="20%"> GTS0</td>
<td width="80%"> Global tristate zero (output enable)</td>
</tr>
<tr>
<td width="20%"> GTS1</td>
<td width="80%"> Global tristate one (output enable)</td>
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<td width="20%"> GTS2</td>
<td width="80%"> Global tristate two (output enable)</td>
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<td width="20%"> GTS3</td>
<td width="80%"> Global tristate three (output enable)</td>
</tr>
<tr>
<td width="20%"> HSTL</td>
<td width="80%"> High speed Tranciever Logic</td>
</tr>
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<td width="20%"> I/O</td>
<td width="80%"> Input/Output</td>
</tr>
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<td width="20%"> INIT</td>
<td width="80%"> Initial state</td>
</tr>
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<td width="20%"> ISP</td>
<td width="80%"> The use of the JTAG port to program the chip while it is powered in a system.</td>
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<td width="20%"> JTAG</td>
<td width="80%"> IEEE Standard 1149 (JTAG) boundary-scan test standard.</td>
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<td width="20%"> KPR</td>
<td width="80%"> Unused I/O with weak keeper (leave unconnected)</td>
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<td width="20%"> NC</td>
<td width="80%"> Not Connected, unbonded pin</td>
</tr>
<tr>
<td width="20%"> PGND</td>
<td width="80%"> Programmable ground pin</td>
</tr>
<tr>
<td width="20%"> PROHIBITED</td>
<td width="80%"> User reserved pin</td>
</tr>
<tr>
<td width="20%"> R</td>
<td width="80%"> Reset</td>
</tr>
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<td width="20%"> S</td>
<td width="80%"> Set</td>
</tr>
<tr>
<td width="20%"> -S</td>
<td width="80%"> Schmitt trigger input (used with VREF input). Schmitt Trigger 1.5 Volts input only. All inputs set to SCHMITT15IN are automatically configured as schmitt-trigger. LVCMOS15 is allowed only on output-only pins. SCHMITT15IN can be used on any type of pad; output requirements are same as for LVCMOS15.</td>
</tr>
<tr>
<td width="20%"> TCK</td>
<td width="80%"> One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. Test operations of the device are synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pull-up forces TCK to a high level if left unconnected.</td>
</tr>
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<td width="20%"> TDI</td>
<td width="80%"> One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial input for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level if left unconnected.</td>
</tr>
<tr>
<td width="20%"> TDO</td>
<td width="80%"> One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial output for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level when it is not driven from an external source.</td>
</tr>
<tr>
<td width="20%"> TIE</td>
<td width="80%"> Unused I/O floating -- must tie to VCC, GND or other signal</td>
</tr>
<tr>
<td width="20%"> TMS</td>
<td width="80%"> One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It directs the device through its Test Access Port controller states. An internal pull-up forces TDI to a high level when it is not driven from an external source. TMS also provides the optional test reset signal of IEEE Std 1149 or IEEE Std 1532.</td>
</tr>
<tr>
<td width="20%"> VAUX</td>
<td width="80%"> JTAG port auxiliary supply voltage</td>
</tr>
<tr>
<td width="20%"> LVCMOS15</td>
<td width="80%"> External Output supply voltage for LVCMOS15</td>
</tr>
<tr>
<td width="20%"> LVCMOS18</td>
<td width="80%"> External I/O supply voltage for LVCMOS18</td>
</tr>
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<td width="20%"> LVCMOS25</td>
<td width="80%"> External I/O supply voltage for LVCMOS25</td>
</tr>
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<td width="20%"> LVCMOS33</td>
<td width="80%"> External I/O supply voltage for LVCMOS33</td>
</tr>
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<td width="20%"> LVTTL</td>
<td width="80%"> Low Voltage Transistor Transistor Logic 3.3Volts</td>
</tr>
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<td width="20%"> SCHMITT15IN</td>
<td width="80%"> Schmitt Trigger 1.5 Volts input only. All inputs set to SCHMITT15IN are automatically configured as schmitt-trigger. LVCMOS15 is allowed only on output-only pins. SCHMITT15IN can be used on any type of pad; output requirements are same as for LVCMOS15.</td>
</tr>
<tr>
<td width="20%"> SSTL</td>
<td width="80%"> Stub Switched Tranceiver Logic</td>
</tr>
<tr>
<td width="20%"> VCCIO</td>
<td width="80%"> External power for Inputs/Outputs</td>
</tr>
<tr>
<td width="20%"> VCCIO-1.5</td>
<td width="80%"> External I/O supply voltage for LVCMOS15, HSTL_I</td>
</tr>
<tr>
<td width="20%"> VCCIO-1.8</td>
<td width="80%"> External I/O supply voltage for LVCMOS18</td>
</tr>
<tr>
<td width="20%"> VCCIO-2.5</td>
<td width="80%"> External I/O supply voltage for LVCMOS25, SSTL2_I</td>
</tr>
<tr>
<td width="20%"> VCCIO-3.3</td>
<td width="80%"> External I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I</td>
</tr>
<tr>
<td width="20%"> VCC</td>
<td width="80%"> Dedicated Power Pin, Internal supply voltage for the device</td>
</tr>
<tr>
<td width="20%"> VREF-[iostd]</td>
<td width="80%"> Reference voltage for indicated input/output standard</td>
</tr>
<tr>
<td width="20%"> *VREF-[iostd]</td>
<td width="80%"> Reference voltage pin selected by software</td>
</tr>
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<td width="20%"> WPU</td>
<td width="80%"> Unused I/O with Internal Weak Pull Up (leave unconnected)</td>
</tr>
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