Subversion Repositories cpu8080

version 3
C:/Xilinx/ISEexamples/cpu8080/testbench.v
testbench
VERILOG
VERILOG
cpu_tbw.xwv
Clocked
-
-
10000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clock
100000000
100000000
15000000
15000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
addr
clock
data
clock
inta
clock
intr
clock
junk
clock
readio
clock
readmem
clock
reset
clock
waitr
clock
writeio
clock
writemem
clock
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
addr_DIFF
inta_DIFF
readio_DIFF
readmem_DIFF
writeio_DIFF
writemem_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clock
intr
reset
waitr
inta
readio
readmem
writeio
writemem
addr
data
SIGNAL_ORDER_END
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