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https://opencores.org/ocsvn/cpu8080/cpu8080/trunk
Subversion Repositories cpu8080
[/] [cpu8080/] [trunk/] [project/] [cpu_tbw.xwv_bak] - Rev 33
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waitr writeio writeio_DIFF writemem writemem_DIFF hsync_n hsync_n_DIFF vsync_n vsync_n_DIFF addr addr /testbench/addr addr_DIFF addr_DIFF /testbench/addr_DIFF data data /testbench/data b b /testbench/b b_DIFF b_DIFF /testbench/b_DIFF g g /testbench/g g_DIFF g_DIFF /testbench/g_DIFF ! r " r /testbench/r! ! # r_DIFF $ r_DIFF /testbench/r_DIFF# # clock /testbench/clock inta /testbench/inta inta_DIFF /testbench/inta_DIFF intr /testbench/intr intr_DIFF /testbench/intr_DIFF readio /testbench/readio readio_DIFF /testbench/readio_DIFF readmem /testbench/readmem readmem_DIFF /testbench/readmem_DIFF reset /testbench/resetwaitr /testbench/waitrwriteio /testbench/writeio writeio_DIFF /testbench/writeio_DIFF writemem /testbench/writemem writemem_DIFF /testbench/writemem_DIFF hsync_n /testbench/hsync_n hsync_n_DIFF /testbench/hsync_n_DIFF vsync_n /testbench/vsync_n vsync_n_DIFF /testbench/vsync_n_DIFF addr /testbench/addr ! " # addr_DIFF /testbench/addr_DIFF$ % & ' ( ) * + , - . / 0 1 2 3 4 data /testbench/data5 6 7 8 9 : ; < = b /testbench/b> ? @ A b_DIFF /testbench/b_DIFFB C D E g /testbench/gF G H I g_DIFF /testbench/g_DIFFJפ8[|P<rVh\kگLе-ƻ