OpenCores
URL https://opencores.org/ocsvn/cpu8080/cpu8080/trunk

Subversion Repositories cpu8080

[/] [cpu8080/] [trunk/] [project/] [isim/] [unisim.auxlib/] [vcomponents/] [vcomponents.h] - Rev 33

Compare with Previous | Blame | View Log

////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /---/   /\     
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////
 
#ifndef H_Unisim_vcomponents_H
#define H_Unisim_vcomponents_H
 
#ifdef __MINGW32__
#include "xsimMinGW.h"
#else
#include "xsim.h"
#endif
 
 
#include "ieee/std_logic_1164/std_logic_1164.h"
 
class Unisim_vcomponents: public HSim__s6 {
public:
    HSim__s1 Sc;
    HSim__s1 Se;
    HSim__s1 Sg;
    HSim__s1 Si;
    HSim__s1 Sk;
    HSim__s1 Sn;
    HSim__s1 Sq;
    HSim__s1 Ss;
    HSim__s1 Su;
    HSim__s1 Sw;
    HSim__s1 Sy;
    HSim__s1 SA;
    HSim__s1 SC;
    HSim__s1 SE;
    HSim__s1 SG;
    HSim__s1 SI;
    HSim__s1 SK;
    HSim__s1 SM;
    HSim__s1 SP;
    HSim__s1 SR;
  Unisim_vcomponents(const HSimString &name);
  ~Unisim_vcomponents();
};
 
extern Unisim_vcomponents *UnisimVcomponents;
 
#endif
 

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.