Subversion Repositories cpu8080

Release 8.2.02i - netgen I.33
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

Command Line: netgen -intstyle ise -s 4 -pcf testbench.pcf -sdf_anno true
-sdf_path netgen/par -insert_glbl true -w -dir netgen/par -ofmt verilog -sim
testbench.ncd testbench_timesim.v  

Read and Annotate design 'testbench.ncd' ...
Loading device for application Rf_Device from file '3s1000.nph' in environment
C:\Xilinx.
   "testbench" is an NCD, version 3.1, device xc3s1000, package ft256, speed -4
Loading constraints from 'testbench.pcf'...
The speed grade (-4) differs from the speed grade specified in the .ncd file
(-4).
The number of routable networks is 5271
Flattening design ...
Processing design ... 
  Preping design's networks ...
  Preping design's macros ...
Writing Verilog SDF file 'netgen\par\testbench_timesim.sdf' ...
Writing Verilog netlist file
'C:\Xilinx\ISEexamples\cpu8080\netgen\par\testbench_timesim.v' ...
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx SIMPRIM
   simulation primitives and has to be used with SIMPRIM simulation library for
   correct compilation and simulation. 
Number of warnings: 0
Number of info messages: 1
Total memory usage is 217748 kilobytes