Subversion Repositories cpu8080

Release 8.2.02i - netgen I.33
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

Command Line: netgen -intstyle ise -insert_glbl true -w -dir netgen/synthesis
-ofmt verilog -sim testbench.ngc _synthesis.v  

Reading design 'testbench.ngc' ...
Flattening design ...
Processing design ... 
  Preping design's networks ...
  Preping design's macros ...
Writing Verilog netlist file
'C:\Xilinx\ISEexamples\cpu8080\netgen\synthesis\_synthesis.v' ...
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx UNISIM
   simulation primitives and has to be used with UNISIM simulation library for
   correct compilation and simulation. 
Number of warnings: 0
Number of info messages: 1
Total memory usage is 57836 kilobytes