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[/] [cpu8080/] [trunk/] [project/] [testbench.bgn] - Rev 20
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Release 8.2.02i - Bitgen I.33
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '3s1000.nph' in environment
C:\Xilinx.
"testbench" is an NCD, version 3.1, device xc3s1000, package ft256, speed -4
Opened constraints file testbench.pcf.
Wed Nov 15 08:55:02 2006
C:\Xilinx\bin\nt\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:6 -g CclkPin:PullNone -g M0Pin:PullNone -g M1Pin:PullNone -g M2Pin:PullNone -g ProgPin:PullNone -g DonePin:PullNone -g TckPin:PullNone -g TdiPin:PullNone -g TdoPin:PullNone -g TmsPin:PullNone -g UnusedPin:PullNone -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Match_cycle:Auto -g Security:None -g DonePipe:No -g DriveDone:No testbench.ncd
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable** |
+----------------------+----------------------+
| DebugBitstream | No** |
+----------------------+----------------------+
| ConfigRate | 6** |
+----------------------+----------------------+
| StartupClk | Cclk** |
+----------------------+----------------------+
| DCMShutdown | Disable** |
+----------------------+----------------------+
| DCIUpdateMode | AsRequired** |
+----------------------+----------------------+
| CclkPin | Pullnone |
+----------------------+----------------------+
| DonePin | Pullnone |
+----------------------+----------------------+
| HswapenPin | Pullup* |
+----------------------+----------------------+
| M0Pin | Pullnone |
+----------------------+----------------------+
| M1Pin | Pullnone |
+----------------------+----------------------+
| M2Pin | Pullnone |
+----------------------+----------------------+
| ProgPin | Pullnone |
+----------------------+----------------------+
| TckPin | Pullnone |
+----------------------+----------------------+
| TdiPin | Pullnone |
+----------------------+----------------------+
| TdoPin | Pullnone |
+----------------------+----------------------+
| TmsPin | Pullnone |
+----------------------+----------------------+
| UnusedPin | Pullnone |
+----------------------+----------------------+
| GWE_cycle | 6** |
+----------------------+----------------------+
| GTS_cycle | 5** |
+----------------------+----------------------+
| LCK_cycle | NoWait** |
+----------------------+----------------------+
| Match_cycle | Auto** |
+----------------------+----------------------+
| DONE_cycle | 4** |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No** |
+----------------------+----------------------+
| DonePipe | No** |
+----------------------+----------------------+
| Security | None** |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF** |
+----------------------+----------------------+
| ActivateGclk | No* |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| PartialMask0 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask1 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask2 | (Not Specified)* |
+----------------------+----------------------+
| PartialGclk | (Not Specified)* |
+----------------------+----------------------+
| PartialLeft | (Not Specified)* |
+----------------------+----------------------+
| PartialRight | (Not Specified)* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No** |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
Running DRC.
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:812 - Dangling pin <DOA5> on
block:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB1
6A>.
WARNING:PhysDesignRules:812 - Dangling pin <DOA6> on
block:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB1
6A>.
WARNING:PhysDesignRules:812 - Dangling pin <DOA7> on
block:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB1
6A>.
DRC detected 0 errors and 7 warnings.
Creating bit map...
Saving bit stream in "testbench.bit".
Bitstream generation is complete.
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