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[/] [cpu8080/] [trunk/] [project/] [testbench.drc] - Rev 20
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 issourced by a combinatorial pin. This is not good design practice. Use the CEpin to control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 issourced by a combinatorial pin. This is not good design practice. Use the CEpin to control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 issourced by a combinatorial pin. This is not good design practice. Use the CEpin to control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 issourced by a combinatorial pin. This is not good design practice. Use the CEpin to control the loading of data into the flip-flop.WARNING:PhysDesignRules:812 - Dangling pin <DOA5> onblock:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA6> onblock:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA7> onblock:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB16A>.DRC detected 0 errors and 7 warnings.
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