Subversion Repositories cpu8080

Release 8.2.02i par I.33
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

SCOTT-H-PC::  Wed Nov 01 08:45:45 2006

par -w -intstyle ise -ol std -t 1 testbench_map.ncd testbench.ncd testbench.pcf


Constraints file: testbench.pcf.
Loading device for application Rf_Device from file '3s1000.nph' in environment C:\Xilinx.
   "testbench" is an NCD, version 3.1, device xc3s1000, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
   the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high". For a
   balance between the fastest runtime and best performance, set the effort level to "med".

Device speed data version:  "PRODUCTION 1.39 2006-07-07".


Device Utilization Summary:

   Number of BUFGMUXs                  3 out of 8      37%
   Number of External IOBs            44 out of 173    25%
      Number of LOCed IOBs            44 out of 44    100%

   Number of MULT18X18s                1 out of 24      4%
   Number of RAMB16s                   2 out of 24      8%
   Number of Slices                 3425 out of 7680   44%
      Number of SLICEMs              950 out of 3840   24%



Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:996b76) REAL time: 9 secs 

Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 10 secs 

Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 10 secs 

Phase 4.2
......
..................


Phase 4.2 (Checksum:98bdbb) REAL time: 22 secs 

Phase 5.8
......................................................................................................................................................................................................................................
..............
.......................................................................................................................
.................
....................
.........................................................
Phase 5.8 (Checksum:ad58a9) REAL time: 3 mins 6 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 3 mins 6 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 4 mins 29 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 4 mins 29 secs 

Writing design to file testbench.ncd


Total REAL time to Placer completion: 4 mins 34 secs 
Total CPU time to Placer completion: 3 mins 57 secs 

Starting Router

Phase 1: 26573 unrouted;       REAL time: 4 mins 34 secs 

Phase 2: 24811 unrouted;       REAL time: 4 mins 40 secs 

Phase 3: 7304 unrouted;       REAL time: 4 mins 47 secs 

Phase 4: 7304 unrouted; (26511)      REAL time: 4 mins 48 secs 

Phase 5: 7292 unrouted; (0)      REAL time: 4 mins 53 secs 

Phase 6: 0 unrouted; (0)      REAL time: 5 mins 11 secs 

Phase 7: 0 unrouted; (0)      REAL time: 5 mins 15 secs 

WARNING:Route:447 - CLK Net:reset_n_BUFGP may have excessive skew because 
   332 NON-CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:clkdiv<3> may have excessive skew because 
   1 NON-CLK pins failed to route using a CLK template.

Total REAL time to Router completion: 5 mins 15 secs 
Total CPU time to Router completion: 4 mins 34 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|       reset_n_BUFGP |      BUFGMUX5| No   |  348 |  0.159     |  1.033      |
+---------------------+--------------+------+------+------------+-------------+
|           clkdiv<3> |      BUFGMUX2| No   |  287 |  0.436     |  1.140      |
+---------------------+--------------+------+------+------------+-------------+
|         clock_BUFGP |      BUFGMUX0| No   | 1266 |  0.519     |  1.221      |
+---------------------+--------------+------+------+------------+-------------+
|select1/selectd/_and |              |      |      |            |             |
|                0000 |         Local|      |    7 |  0.011     |  2.195      |
+---------------------+--------------+------+------+------------+-------------+
|select1/selecta/_and |              |      |      |            |             |
|                0000 |         Local|      |    7 |  0.143     |  3.148      |
+---------------------+--------------+------+------+------------+-------------+
|select1/selectb/_and |              |      |      |            |             |
|                0000 |         Local|      |    7 |  0.066     |  2.239      |
+---------------------+--------------+------+------+------------+-------------+
|select1/selectc/_and |              |      |      |            |             |
|                0000 |         Local|      |    7 |  0.120     |  2.850      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        2.120
   The MAXIMUM PIN DELAY IS:                              12.443
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   9.291

   Listing Pin Delays by value: (nsec)

    d < 2.00   < d < 4.00  < d < 6.00  < d < 8.00  < d < 13.00  d >= 13.00
   ---------   ---------   ---------   ---------   ---------   ---------
       15385        8001        2840         587          73           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of
                                            |            |            | Levels | Slack      |errors   
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | N/A        | 23.680ns   | 3      | N/A        | N/A     
  div<3>                                    |            |            |        |            |         
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clo | N/A        | 33.066ns   | 12     | N/A        | N/A     
  ck_BUFGP                                  |            |            |        |            |         
------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the 
   constraint does not cover any paths or that it has no requested value.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 mins 25 secs 
Total CPU time to PAR completion: 4 mins 42 secs 

Peak Memory Usage:  263 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 2
Number of info messages: 1

Writing design to file testbench.ncd



PAR done!