Subversion Repositories cpu8080

Release 8.2.02i - xst I.33
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.19 s | Elapsed : 0.00 / 0.00 s
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/common.vhd" in Library work.
Architecture common of Entity common is up to date.
Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/vga.vhd" in Library work.
Architecture vga_arch of Entity vga is up to date.
Architecture sync_arch of Entity sync is up to date.
Compiling verilog file "vgachr.v" in library work
Module <terminal> compiled
Module <chrmemmap> compiled
Compiling verilog file "cpu8080.v" in library work
Module <chrrom> compiled
Module <cpu8080> compiled
Compiling verilog file "testbench.v" in library work
Module <alu> compiled
Module <testbench> compiled
Module <select> compiled
Module <selectone> compiled
Module <intcontrol> compiled
Compiling verilog include file "test.lst"
Module <rom> compiled
Module <ram> compiled
No errors in compilation
Analysis of file <"testbench.prj"> succeeded.
 
CPU : 0.56 / 0.75 s | Elapsed : 0.00 / 0.00 s
 
--> 

Total memory usage is 112740 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)