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[/] [cpu8080/] [trunk/] [project/] [testbench.stx] - Rev 20

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Release 8.2.02i - xst I.33
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.25 s | Elapsed : 0.00 / 0.00 s
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/common.vhd" in Library work.
Architecture common of Entity common is up to date.
Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/ps2_kbd.vhd" in Library work.
Architecture arch of Entity ps2_kbd is up to date.
Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/vga.vhd" in Library work.
Package <vga_pckg> compiled.
Entity <vga> compiled.
Entity <vga> (Architecture <vga_arch>) compiled.
Entity <sync> compiled.
Entity <sync> (Architecture <sync_arch>) compiled.
Compiling verilog file "vgachr.v" in library work
Module <terminal> compiled
Module <chrmemmap> compiled
Module <chrrom> compiled
Module <scnrom> compiled
Compiling verilog file "cpu8080.v" in library work
Module <scnromu> compiled
Module <cpu8080> compiled
Compiling verilog file "testbench.v" in library work
Module <alu> compiled
Module <testbench> compiled
Module <select> compiled
Module <selectone> compiled
Module <intcontrol> compiled
Compiling verilog include file "test.rom"
Module <rom> compiled
Module <ram> compiled
No errors in compilation
Analysis of file <"testbench.prj"> succeeded.
 
CPU : 0.88 / 1.13 s | Elapsed : 1.00 / 1.00 s
 
--> 

Total memory usage is 113764 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

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