URL
https://opencores.org/ocsvn/cpu8080/cpu8080/trunk
Subversion Repositories cpu8080
[/] [cpu8080/] [trunk/] [project/] [testbench.syr] - Rev 20
Go to most recent revision | Compare with Previous | Blame | View Log
Release 8.2.02i - xst I.33Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to ./xst/projnav.tmpCPU : 0.00 / 0.39 s | Elapsed : 0.00 / 0.00 s--> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.39 s | Elapsed : 0.00 / 0.00 s--> Reading design: testbench.prjTABLE OF CONTENTS1) Synthesis Options Summary2) HDL Compilation3) Design Hierarchy Analysis4) HDL Analysis5) HDL Synthesis5.1) HDL Synthesis Report6) Advanced HDL Synthesis6.1) Advanced HDL Synthesis Report7) Low Level Synthesis8) Partition Report9) Final Report9.1) Device utilization summary9.2) TIMING REPORT=========================================================================* Synthesis Options Summary *=========================================================================---- Source ParametersInput File Name : "testbench.prj"Input Format : mixedIgnore Synthesis Constraint File : NO---- Target ParametersOutput File Name : "testbench"Output Format : NGCTarget Device : xc3s1000-4-ft256---- Source OptionsTop Module Name : testbenchAutomatic FSM Extraction : YESFSM Encoding Algorithm : AutoFSM Style : lutRAM Extraction : YesRAM Style : AutoROM Extraction : YesMux Style : AutoDecoder Extraction : YESPriority Encoder Extraction : YESShift Register Extraction : YESLogical Shifter Extraction : YESXOR Collapsing : YESROM Style : AutoMux Extraction : YESResource Sharing : YESMultiplier Style : autoAutomatic Register Balancing : No---- Target OptionsAdd IO Buffers : YESGlobal Maximum Fanout : 500Add Generic Clock Buffer(BUFG) : 8Register Duplication : YESSlice Packing : YESPack IO Registers into IOBs : autoEquivalent register Removal : YES---- General OptionsOptimization Goal : SpeedOptimization Effort : 1Keep Hierarchy : NORTL Output : YesGlobal Optimization : AllClockNetsWrite Timing Constraints : NOHierarchy Separator : /Bus Delimiter : <>Case Specifier : maintainSlice Utilization Ratio : 100Slice Utilization Ratio Delta : 5---- Other Optionslso : testbench.lsoRead Cores : YEScross_clock_analysis : NOverilog2001 : YESsafe_implementation : NoOptimize Instantiated Primitives : NOuse_clock_enable : Yesuse_sync_set : Yesuse_sync_reset : Yes==================================================================================================================================================* HDL Compilation *=========================================================================Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/common.vhd" in Library work.Architecture common of Entity common is up to date.Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/ps2_kbd.vhd" in Library work.Architecture arch of Entity ps2_kbd is up to date.Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/vga.vhd" in Library work.Package <vga_pckg> compiled.Entity <vga> compiled.Entity <vga> (Architecture <vga_arch>) compiled.Entity <sync> compiled.Entity <sync> (Architecture <sync_arch>) compiled.Compiling verilog file "vgachr.v" in library workModule <terminal> compiledModule <chrmemmap> compiledModule <chrrom> compiledModule <scnrom> compiledCompiling verilog file "cpu8080.v" in library workModule <scnromu> compiledModule <cpu8080> compiledCompiling verilog file "testbench.v" in library workModule <alu> compiledModule <testbench> compiledModule <select> compiledModule <selectone> compiledModule <intcontrol> compiledCompiling verilog include file "test.rom"Module <rom> compiledModule <ram> compiledNo errors in compilationAnalysis of file <"testbench.prj"> succeeded.=========================================================================* Design Hierarchy Analysis *=========================================================================Analyzing hierarchy for module <testbench> in library <work>.Analyzing hierarchy for module <select> in library <work>.Analyzing hierarchy for module <cpu8080> in library <work>.Analyzing hierarchy for module <rom> in library <work>.Analyzing hierarchy for module <ram> in library <work>.Analyzing hierarchy for module <intcontrol> in library <work>.Analyzing hierarchy for module <terminal> in library <work>.Analyzing hierarchy for module <selectone> in library <work>.Analyzing hierarchy for module <alu> in library <work>.Analyzing hierarchy for module <chrmemmap> in library <work>.Analyzing hierarchy for entity <ps2_kbd> in library <work> (architecture <arch>) with generics.FREQ = 50000Analyzing hierarchy for module <scnrom> in library <work>.Analyzing hierarchy for module <scnromu> in library <work>.Analyzing hierarchy for entity <vga> in library <work> (architecture <vga_arch>) with generics.CLK_DIV = 2FIT_TO_SCREEN = trueFREQ = 50000LINES_PER_FRAME = 480NUM_RGB_BITS = 3PIXEL_WIDTH = 1PIXELS_PER_LINE = 640Analyzing hierarchy for module <chrrom> in library <work>.Analyzing hierarchy for entity <sync> in library <work> (architecture <sync_arch>) with generics.FREQ = 25000PERIOD = 32START = 26VISIBLE = 640WIDTH = 4Analyzing hierarchy for entity <sync> in library <work> (architecture <sync_arch>) with generics.FREQ = 31PERIOD = 16784START = 15700VISIBLE = 480WIDTH = 64Building hierarchy successfully finished.=========================================================================* HDL Analysis *=========================================================================Analyzing top module <testbench>.Module <testbench> is correct for synthesis.Analyzing module <select> in library <work>.Module <select> is correct for synthesis.Analyzing module <selectone> in library <work>.Module <selectone> is correct for synthesis.Analyzing module <cpu8080> in library <work>.Module <cpu8080> is correct for synthesis.Analyzing module <alu> in library <work>.Module <alu> is correct for synthesis.Analyzing module <rom> in library <work>.Module <rom> is correct for synthesis.Analyzing module <ram> in library <work>.Module <ram> is correct for synthesis.Analyzing module <intcontrol> in library <work>.Module <intcontrol> is correct for synthesis.Analyzing module <terminal> in library <work>.Module <terminal> is correct for synthesis.Analyzing module <chrmemmap> in library <work>.Module <chrmemmap> is correct for synthesis.Analyzing generic Entity <vga> in library <work> (Architecture <vga_arch>).PIXEL_WIDTH = 1PIXELS_PER_LINE = 640CLK_DIV = 2FIT_TO_SCREEN = trueFREQ = 50000LINES_PER_FRAME = 480NUM_RGB_BITS = 3Entity <vga> analyzed. Unit <vga> generated.Analyzing generic Entity <sync.1> in library <work> (Architecture <sync_arch>).FREQ = 25000VISIBLE = 640WIDTH = 4PERIOD = 32START = 26Entity <sync.1> analyzed. Unit <sync.1> generated.Analyzing generic Entity <sync.2> in library <work> (Architecture <sync_arch>).FREQ = 31PERIOD = 16784START = 15700VISIBLE = 480WIDTH = 64Entity <sync.2> analyzed. Unit <sync.2> generated.Analyzing module <chrrom> in library <work>.Module <chrrom> is correct for synthesis.Analyzing generic Entity <ps2_kbd> in library <work> (Architecture <arch>).FREQ = 50000Entity <ps2_kbd> analyzed. Unit <ps2_kbd> generated.Analyzing module <scnrom> in library <work>.Module <scnrom> is correct for synthesis.Analyzing module <scnromu> in library <work>.Module <scnromu> is correct for synthesis.=========================================================================* HDL Synthesis *=========================================================================Performing bidirectional port resolution...Synthesizing Unit <rom>.Related source file is "testbench.v".Found 128x8-bit ROM for signal <$mux0000>.Found 8-bit tristate buffer for signal <data>.Summary:inferred 1 ROM(s).inferred 8 Tristate(s).Unit <rom> synthesized.Synthesizing Unit <ram>.Related source file is "testbench.v".Found 1024x8-bit single-port block RAM for signal <ramcore>.-----------------------------------------------------------------------| ram_style | Auto | |-----------------------------------------------------------------------| Port A || aspect ratio | 1024-word x 8-bit | || mode | read-first | || clkA | connected to signal <clock> | fall || enA | connected to signal <select> | high || weA | connected to signal <write> | high || addrA | connected to signal <addr> | || diA | connected to signal <data> | || doA | connected to signal <datao> | |-----------------------------------------------------------------------Found 8-bit tristate buffer for signal <data>.Summary:inferred 1 RAM(s).inferred 8 Tristate(s).Unit <ram> synthesized.Synthesizing Unit <intcontrol>.Related source file is "testbench.v".Found finite state machine <FSM_0> for signal <state>.-----------------------------------------------------------------------| States | 3 || Transitions | 3 || Inputs | 0 || Outputs | 4 || Clock | clock (falling_edge) || Clock enable | $not0004 (positive) || Reset | reset (positive) || Reset type | synchronous || Reset State | 0000 || Encoding | automatic || Implementation | LUT |-----------------------------------------------------------------------Found 8-bit tristate buffer for signal <data>.Found 1-bit 4-to-1 multiplexer for signal <$mux0000>.Found 1-bit 4-to-1 multiplexer for signal <$mux0001>.Found 1-bit 4-to-1 multiplexer for signal <$mux0002>.Found 1-bit 4-to-1 multiplexer for signal <$mux0003>.Found 1-bit 4-to-1 multiplexer for signal <$mux0004>.Found 1-bit 4-to-1 multiplexer for signal <$mux0005>.Found 1-bit 4-to-1 multiplexer for signal <$mux0006>.Found 1-bit 4-to-1 multiplexer for signal <$mux0007>.Found 8-bit register for signal <active>.Found 8-bit register for signal <datai>.Found 8-bit register for signal <edges>.Found 8-bit register for signal <mask>.Found 8-bit register for signal <polarity>.Found 8-bit register for signal <vbase>.Summary:inferred 1 Finite State Machine(s).inferred 48 D-type flip-flop(s).inferred 8 Multiplexer(s).inferred 8 Tristate(s).Unit <intcontrol> synthesized.Synthesizing Unit <selectone>.Related source file is "testbench.v".WARNING:Xst:647 - Input <addr<9:8>> is never used.WARNING:Xst:647 - Input <addr<1>> is never used.WARNING:Xst:737 - Found 6-bit latch for signal <comp>.WARNING:Xst:737 - Found 8-bit latch for signal <mask>.WARNING:Xst:737 - Found 8-bit latch for signal <datai>.Found 8-bit tristate buffer for signal <data>.Found 6-bit comparator equal for signal <$cmp_eq0000> created at line 291.Summary:inferred 1 Comparator(s).inferred 8 Tristate(s).Unit <selectone> synthesized.Synthesizing Unit <alu>.Related source file is "cpu8080.v".WARNING:Xst:646 - Signal <resi> is assigned but never used.Found 1-bit 8-to-1 multiplexer for signal <cout>.Found 1-bit 8-to-1 multiplexer for signal <auxcar>.Found 5-bit adder for signal <$add0001> created at line 1514.Found 8-bit adder carry out for signal <$addsub0000> created at line 1507.Found 4-bit adder carry out for signal <$addsub0001> created at line 1508.Found 6-bit subtractor for signal <$sub0000> created at line 1520.Found 6-bit subtractor for signal <$sub0001> created at line 1526.Found 9-bit subtractor for signal <$sub0002> created at line 1519.Found 8-bit xor2 for signal <$xor0000> created at line 1537.Found 1-bit xor8 for signal <$xor0002>.Summary:inferred 8 Adder/Subtractor(s).inferred 10 Multiplexer(s).inferred 1 Xor(s).Unit <alu> synthesized.Synthesizing Unit <ps2_kbd>.Related source file is "C:/Xilinx/ISEexamples/cpu8080/ps2_kbd.vhd".WARNING:Xst:646 - Signal <keyrel_r> is assigned but never used.Found 13-bit adder for signal <$addsub0000> created at line 112.Found 4-bit up counter for signal <bitcnt_r>.Found 1-bit register for signal <error_r>.Found 5-bit register for signal <ps2_clk_r>.Found 1-bit register for signal <rdy_r>.Found 10-bit register for signal <sc_r>.Found 13-bit register for signal <timer_r>.Summary:inferred 1 Counter(s).inferred 30 D-type flip-flop(s).inferred 1 Adder/Subtractor(s).Unit <ps2_kbd> synthesized.Synthesizing Unit <scnrom>.Related source file is "vgachr.v".Unit <scnrom> synthesized.Synthesizing Unit <scnromu>.Related source file is "vgachr.v".Unit <scnromu> synthesized.Synthesizing Unit <chrrom>.Related source file is "vgachr.v".Found 2048x8-bit ROM for signal <data>.Summary:inferred 1 ROM(s).Unit <chrrom> synthesized.Synthesizing Unit <sync_1>.Related source file is "C:/Xilinx/ISEexamples/cpu8080/vga.vhd".Found 16-bit adder for signal <$addsub0000> created at line 398.Found 1-bit register for signal <blank_r>.Found 16-bit register for signal <cnt_r>.Found 1-bit register for signal <gate_r>.Found 1-bit register for signal <sync_r>.Summary:inferred 3 D-type flip-flop(s).inferred 1 Adder/Subtractor(s).Unit <sync_1> synthesized.Synthesizing Unit <sync_2>.Related source file is "C:/Xilinx/ISEexamples/cpu8080/vga.vhd".Found 16-bit adder for signal <$addsub0000> created at line 398.Found 1-bit register for signal <blank_r>.Found 16-bit register for signal <cnt_r>.Found 1-bit register for signal <gate_r>.Found 1-bit register for signal <sync_r>.Summary:inferred 3 D-type flip-flop(s).inferred 1 Adder/Subtractor(s).Unit <sync_2> synthesized.Synthesizing Unit <select>.Related source file is "testbench.v".Found 1-bit register for signal <bootstrap>.Found 8-bit tristate buffer for signal <data>.Found 8-bit register for signal <datai>.Found 4-bit comparator equal for signal <selacc>.Found 4-bit register for signal <seladr>.Summary:inferred 13 D-type flip-flop(s).inferred 1 Comparator(s).inferred 8 Tristate(s).Unit <select> synthesized.Synthesizing Unit <cpu8080>.Related source file is "cpu8080.v".INFO:Xst:1799 - State 0XXXXX is never reached in FSM <state>.Found finite state machine <FSM_1> for signal <state>.-----------------------------------------------------------------------| States | 34 || Transitions | 901 || Inputs | 139 || Outputs | 33 || Clock | clock (rising_edge) || Reset | reset (positive) || Reset type | synchronous || Reset State | 000001 || Encoding | automatic || Implementation | LUT |-----------------------------------------------------------------------Found 4x1-bit ROM for signal <$mux0043> created at line 309.Found 16-bit register for signal <addr>.Found 1-bit register for signal <writeio>.Found 1-bit register for signal <readio>.Found 1-bit register for signal <writemem>.Found 1-bit register for signal <readmem>.Found 1-bit register for signal <inta>.Found 8-bit tristate buffer for signal <data>.Found 32-bit adder for signal <$add0001> created at line 491.Found 32-bit adder for signal <$add0002> created at line 503.Found 32-bit adder for signal <$add0003> created at line 515.Found 16-bit adder for signal <$add0004> created at line 975.Found 16-bit adder for signal <$add0005> created at line 886.Found 32-bit adder for signal <$add0006> created at line 560.Found 32-bit adder for signal <$add0007> created at line 548.Found 32-bit adder for signal <$add0008> created at line 536.Found 17-bit adder for signal <$add0009> created at line 481.Found 17-bit adder for signal <$addsub0000>.Found 17-bit adder for signal <$addsub0001>.Found 17-bit adder for signal <$addsub0002>.Found 8-bit adder for signal <$addsub0003>.Found 8-bit addsub for signal <$addsub0004>.Found 8-bit addsub for signal <$addsub0005>.Found 8-bit addsub for signal <$addsub0006>.Found 16-bit adder for signal <$addsub0007> created at line 1046.Found 6-bit adder for signal <$addsub0008>.Found 16-bit adder for signal <$addsub0009> created at line 1087.Found 8-bit adder carry out for signal <$addsub0010>.Found 4-bit adder carry out for signal <$addsub0011> created at line 356.Found 8-bit adder carry out for signal <$addsub0012>.Found 4-bit comparator greater for signal <$cmp_gt0000> created at line 353.Found 4-bit comparator greater for signal <$cmp_gt0001> created at line 1324.Found 3-bit 4-to-1 multiplexer for signal <$mux0022> created at line 309.Found 8-bit 4-to-1 multiplexer for signal <$mux0023> created at line 309.Found 3-bit 4-to-1 multiplexer for signal <$mux0025> created at line 309.Found 8-bit 4-to-1 multiplexer for signal <$mux0031> created at line 309.Found 3-bit 4-to-1 multiplexer for signal <$mux0045>.Found 3-bit 4-to-1 multiplexer for signal <$mux0050> created at line 313.Found 8-bit 4-to-1 multiplexer for signal <$mux0051>.Found 16-bit adder for signal <$share0000> created at line 309.Found 16-bit addsub for signal <$share0006> created at line 309.Found 32-bit subtractor for signal <$sub0000> created at line 536.Found 32-bit subtractor for signal <$sub0001> created at line 548.Found 32-bit subtractor for signal <$sub0002> created at line 560.Found 16-bit subtractor for signal <$sub0003> created at line 757.Found 1-bit register for signal <alucin>.Found 8-bit register for signal <aluopra>.Found 8-bit register for signal <aluoprb>.Found 3-bit register for signal <alusel>.Found 1-bit register for signal <auxcar>.Found 1-bit register for signal <carry>.Found 1-bit register for signal <dataeno>.Found 8-bit register for signal <datao>.Found 1-bit register for signal <ei>.Found 1-bit register for signal <eienb>.Found 1-bit register for signal <intcyc>.Found 8-bit register for signal <opcode>.Found 1-bit register for signal <parity>.Found 16-bit register for signal <pc>.Found 2-bit register for signal <popdes>.Found 16-bit register for signal <raddrhold>.Found 8-bit register for signal <rdatahold>.Found 8-bit register for signal <rdatahold2>.Found 3-bit register for signal <regd>.Found 64-bit register for signal <regfil>.Found 1-bit register for signal <sign>.Found 16-bit register for signal <sp>.Found 6-bit register for signal <statesel>.Found 16-bit register for signal <waddrhold>.Found 8-bit register for signal <wdatahold>.Found 8-bit register for signal <wdatahold2>.Found 1-bit register for signal <zero>.Summary:inferred 1 Finite State Machine(s).inferred 1 ROM(s).inferred 237 D-type flip-flop(s).inferred 34 Adder/Subtractor(s).inferred 2 Comparator(s).inferred 52 Multiplexer(s).inferred 8 Tristate(s).Unit <cpu8080> synthesized.Synthesizing Unit <vga>.Related source file is "C:/Xilinx/ISEexamples/cpu8080/vga.vhd".WARNING:Xst:646 - Signal <line_cnt> is assigned but never used.WARNING:Xst:646 - Signal <pixel_cnt<15:4>> is assigned but never used.Found 3-bit register for signal <blank_r>.Found 1-bit register for signal <cke>.Found 8-bit up counter for signal <clk_div_cnt>.Found 1-bit register for signal <eof_r>.Found 3-bit register for signal <hsync_r>.Found 16-bit register for signal <pixel_data_r>.Found 1-bit register for signal <rd_r>.Found 9-bit register for signal <rgb_r>.Summary:inferred 1 Counter(s).inferred 34 D-type flip-flop(s).Unit <vga> synthesized.Synthesizing Unit <chrmemmap>.Related source file is "vgachr.v".WARNING:Xst:646 - Signal <curatr<4>> is assigned but never used.WARNING:Xst:646 - Signal <blank> is assigned but never used.Found 1920x8-bit single-port block RAM for signal <scnbuf>.-----------------------------------------------------------------------| ram_style | Auto | |-----------------------------------------------------------------------| Port A || aspect ratio | 1920-word x 8-bit | || mode | read-first | || clkA | connected to signal <clk> | rise || weA | connected to signal <write> | high || addrA | connected to signal <addr> | || diA | connected to signal <data> | || doA | connected to signal <datao> | |-----------------------------------------------------------------------Found 1920x8-bit dual-port distributed RAM for signal <scnbuf>.-----------------------------------------------------------------------| ram_style | Auto | |-----------------------------------------------------------------------| Port A || aspect ratio | 1920-word x 8-bit | || clkA | connected to signal <clk> | rise || weA | connected to signal <write> | high || addrA | connected to signal <addr> | || diA | connected to signal <data> | |-----------------------------------------------------------------------| Port B || aspect ratio | 1920-word x 8-bit | || addrB | connected to internal node | || doB | connected to internal node | |-----------------------------------------------------------------------INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.Found 1920x5-bit dual-port block RAM for signal <atrbuf>.-----------------------------------------------------------------------| ram_style | Auto | |-----------------------------------------------------------------------| Port A || aspect ratio | 1920-word x 5-bit | || mode | read-first | || clkA | connected to signal <clk> | rise || weA | connected to signal <write> | high || addrA | connected to signal <addr> | || diA | connected to signal <attr> | || doA | connected to signal <attro> | |-----------------------------------------------------------------------| Port B || aspect ratio | 1920-word x 5-bit | || mode | read-first | || clkB | connected to signal <clk> | rise || addrB | connected to internal node | || doB | connected to signal <curatr> | |-----------------------------------------------------------------------INFO:Xst:2117 - HDL ADVISOR - Mux Selector <fchsta> of Case statement line 867 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:- add an 'INIT' attribute on signal <fchsta> (optimization is then done without any risk)- use the attribute 'signal_encoding user' to avoid onehot optimization- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimizationFound finite state machine <FSM_2> for signal <fchsta>.-----------------------------------------------------------------------| States | 4 || Transitions | 7 || Inputs | 1 || Outputs | 6 || Clock | clk (rising_edge) || Clock enable | $not0008 (positive) || Reset | rst (positive) || Reset type | synchronous || Reset State | 00 || Encoding | automatic || Implementation | LUT |-----------------------------------------------------------------------WARNING:Xst:643 - "vgachr.v" line 939: The result of a 9x6-bit multiplication is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.Found 5-bit tristate buffer for signal <attr>.Found 8-bit tristate buffer for signal <data>.Found 11-bit adder for signal <$add0000> created at line 922.Found 9-bit subtractor for signal <$addsub0000> created at line 939.Found 11-bit adder for signal <$addsub0001> created at line 939.Found 11-bit comparator equal for signal <$cmp_eq0003> created at line 876.Found 32-bit comparator greatequal for signal <$cmp_ge0000> created at line 808.Found 7-bit comparator greatequal for signal <$cmp_ge0001> created at line 848.Found 5-bit comparator greatequal for signal <$cmp_ge0002> created at line 852.Found 7-bit comparator less for signal <$cmp_lt0000> created at line 848.Found 5-bit comparator less for signal <$cmp_lt0001> created at line 852.Found 8-bit comparator less for signal <$cmp_lt0002> created at line 939.Found 9x6-bit multiplier for signal <$mult0002> created at line 939.Found 16-bit 4-to-1 multiplexer for signal <$mux0000> created at line 905.Found 1-bit 4-to-1 multiplexer for signal <$mux0001> created at line 898.Found 1-bit 4-to-1 multiplexer for signal <$mux0002> created at line 898.Found 1-bit 4-to-1 multiplexer for signal <$mux0003> created at line 898.Found 1-bit 4-to-1 multiplexer for signal <$mux0004> created at line 898.Found 1-bit 4-to-1 multiplexer for signal <$mux0005> created at line 898.Found 1-bit 4-to-1 multiplexer for signal <$mux0006> created at line 898.Found 1-bit 4-to-1 multiplexer for signal <$mux0007> created at line 898.Found 1-bit 4-to-1 multiplexer for signal <$mux0008> created at line 898.Found 8-bit 4-to-1 multiplexer for signal <$mux0009> created at line 877.Found 1-bit xor2 for signal <$xor0000> created at line 897.Found 32-bit up counter for signal <blinkcnt>.Found 1-bit register for signal <blon>.Found 7-bit up counter for signal <chrcnt>.Found 8-bit register for signal <curchr>.Found 5-bit up counter for signal <lincnt>.Found 8-bit register for signal <pixdatl>.Found 16-bit register for signal <pixeldata>.Found 5-bit up counter for signal <rowcnt>.Found 11-bit up accumulator for signal <scnadr>.Summary:inferred 1 Finite State Machine(s).inferred 3 RAM(s).inferred 4 Counter(s).inferred 1 Accumulator(s).inferred 33 D-type flip-flop(s).inferred 3 Adder/Subtractor(s).inferred 1 Multiplier(s).inferred 7 Comparator(s).inferred 32 Multiplexer(s).inferred 13 Tristate(s).Unit <chrmemmap> synthesized.Synthesizing Unit <terminal>.Related source file is "vgachr.v".WARNING:Xst:646 - Signal <parity> is assigned but never used.WARNING:Xst:646 - Signal <cmattri<7:5>> is assigned but never used.WARNING:Xst:646 - Signal <error> is assigned but never used.Register <cmattre> equivalent to <cmdatae> has been removedFound finite state machine <FSM_3> for signal <state>.-----------------------------------------------------------------------| States | 20 || Transitions | 88 || Inputs | 21 || Outputs | 21 || Clock | clock (rising_edge) || Reset | reset (positive) || Reset type | synchronous || Reset State | 00100 || Encoding | automatic || Implementation | LUT |-----------------------------------------------------------------------WARNING:Xst:643 - "vgachr.v" line 682: The result of a 9x8-bit multiplication is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.Found 4x1-bit ROM for signal <$mux0023> created at line 366.Found 8-bit tristate buffer for signal <data>.Found 11-bit adder for signal <$add0002> created at line 552.Found 9-bit subtractor for signal <$addsub0000> created at line 682.Found 11-bit adder for signal <$addsub0001> created at line 515.Found 11-bit adder for signal <$addsub0002>.Found 11-bit adder carry out for signal <$addsub0003> created at line 535.Found 8-bit comparator greatequal for signal <$cmp_ge0000> created at line 378.Found 11-bit comparator greatequal for signal <$cmp_ge0001> created at line 407.Found 8-bit comparator greatequal for signal <$cmp_ge0002> created at line 679.Found 8-bit comparator greatequal for signal <$cmp_ge0003> created at line 352.Found 8-bit comparator greatequal for signal <$cmp_ge0004> created at line 355.Found 12-bit comparator greater for signal <$cmp_gt0000> created at line 535.Found 8-bit comparator greater for signal <$cmp_gt0001> created at line 701.Found 11-bit comparator greater for signal <$cmp_gt0002> created at line 419.Found 12-bit comparator greater for signal <$cmp_gt0003> created at line 535.Found 8-bit comparator lessequal for signal <$cmp_le0000> created at line 679.Found 8-bit comparator lessequal for signal <$cmp_le0001> created at line 679.Found 8-bit comparator lessequal for signal <$cmp_le0002> created at line 352.Found 8-bit comparator lessequal for signal <$cmp_le0003> created at line 355.Found 11-bit comparator less for signal <$cmp_lt0000> created at line 392.Found 11-bit comparator less for signal <$cmp_lt0001> created at line 513.Found 11-bit comparator less for signal <$cmp_lt0002> created at line 549.Found 11-bit comparator less for signal <$cmp_lt0003> created at line 597.Found 8-bit comparator less for signal <$cmp_lt0004> created at line 701.Found 11-bit comparator less for signal <$cmp_lt0005> created at line 426.Found 9x8-bit multiplier for signal <$mult0002> created at line 682.Found 1-bit 4-to-1 multiplexer for signal <$mux0005>.Found 1-bit 8-to-1 multiplexer for signal <$mux0007>.Found 11-bit addsub for signal <$share0000> created at line 366.Found 10-bit subtractor for signal <$sub0000> created at line 682.Found 5-bit subtractor for signal <$sub0001> created at line 702.Found 1-bit register for signal <capslock>.Found 8-bit register for signal <chrdatw>.Found 1-bit register for signal <clrrdy>.Found 11-bit register for signal <cmaddr>.Found 5-bit tristate buffer for signal <cmattr>.Found 8-bit register for signal <cmattri>.Found 8-bit tristate buffer for signal <cmdata>.Found 1-bit register for signal <cmdatae>.Found 8-bit register for signal <cmdatai>.Found 1-bit register for signal <cmread>.Found 1-bit register for signal <cmwrite>.Found 5-bit register for signal <curatr>.Found 11-bit register for signal <cursor>.Found 8-bit register for signal <datao>.Found 1-bit register for signal <extcod>.Found 1-bit register for signal <extkey>.Found 1-bit register for signal <leftctrl>.Found 1-bit register for signal <leftshift>.Found 1-bit register for signal <outrdy>.Found 1-bit register for signal <relcod>.Found 1-bit register for signal <rightctrl>.Found 1-bit register for signal <rightshift>.Found 8-bit register for signal <rowchr>.Found 1-bit register for signal <scnrdy>.Found 11-bit register for signal <tcursor>.Found 1-bit register for signal <wrtchr>.Summary:inferred 1 Finite State Machine(s).inferred 1 ROM(s).inferred 93 D-type flip-flop(s).inferred 8 Adder/Subtractor(s).inferred 1 Multiplier(s).inferred 19 Comparator(s).inferred 2 Multiplexer(s).inferred 21 Tristate(s).Unit <terminal> synthesized.Synthesizing Unit <testbench>.Related source file is "testbench.v".Unit <testbench> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================HDL Synthesis ReportMacro Statistics# RAMs : 41024x8-bit single-port block RAM : 11920x5-bit dual-port block RAM : 11920x8-bit dual-port distributed RAM : 11920x8-bit single-port block RAM : 1# ROMs : 4128x8-bit ROM : 12048x8-bit ROM : 14x1-bit ROM : 2# Multipliers : 29x6-bit multiplier : 19x8-bit multiplier : 1# Adders/Subtractors : 5610-bit subtractor : 111-bit adder : 511-bit adder carry out : 111-bit addsub : 113-bit adder : 116-bit adder : 716-bit addsub : 116-bit subtractor : 117-bit adder : 832-bit adder : 632-bit subtractor : 34-bit adder carry out : 25-bit adder : 15-bit subtractor : 16-bit adder : 16-bit subtractor : 28-bit adder : 18-bit adder carry out : 38-bit addsub : 39-bit adder : 39-bit subtractor : 4# Counters : 632-bit up counter : 14-bit up counter : 15-bit up counter : 27-bit up counter : 18-bit up counter : 1# Accumulators : 111-bit up accumulator : 1# Registers : 1041-bit register : 5110-bit register : 111-bit register : 313-bit register : 116-bit register : 92-bit register : 13-bit register : 44-bit register : 15-bit register : 26-bit register : 18-bit register : 299-bit register : 1# Latches : 126-bit latch : 48-bit latch : 8# Comparators : 3311-bit comparator equal : 111-bit comparator greatequal : 111-bit comparator greater : 111-bit comparator less : 512-bit comparator greater : 232-bit comparator greatequal : 14-bit comparator equal : 14-bit comparator greater : 25-bit comparator greatequal : 15-bit comparator less : 16-bit comparator equal : 47-bit comparator greatequal : 17-bit comparator less : 18-bit comparator greatequal : 48-bit comparator greater : 18-bit comparator less : 28-bit comparator lessequal : 4# Multiplexers : 321-bit 4-to-1 multiplexer : 171-bit 8-to-1 multiplexer : 316-bit 4-to-1 multiplexer : 13-bit 4-to-1 multiplexer : 48-bit 4-to-1 multiplexer : 48-bit 8-to-1 multiplexer : 3# Tristates : 145-bit tristate buffer : 28-bit tristate buffer : 12# Xors : 31-bit xor2 : 11-bit xor8 : 18-bit xor2 : 1==================================================================================================================================================* Advanced HDL Synthesis *=========================================================================Analyzing FSM <FSM_3> for best encoding.Optimizing FSM <adm3a/state> on signal <state[1:20]> with one-hot encoding.-------------------------------State | Encoding-------------------------------00000 | 0000000000000010000000001 | 0000000000000000001000010 | 0000000000000100000000011 | 0000000000001000000000100 | 0000000000000000000100101 | 0000000000010000000000110 | 0000000000100000000000111 | 0000000001000000000001000 | 0000000000000000100001001 | 0000000000000000010001010 | 0000000010000000000001011 | 0000001000000000000001100 | 0000010000000000000001101 | 0000100000000000000001110 | 0000000100000000000001111 | 0001000000000000000010000 | 0000000000000001000010001 | 0010000000000000000010010 | 1000000000000000000010011 | 01000000000000000000-------------------------------Analyzing FSM <FSM_2> for best encoding.Optimizing FSM <adm3a/display/fchsta> on signal <fchsta[1:2]> with gray encoding.-------------------State | Encoding-------------------00 | 0001 | 0110 | 1111 | 10-------------------Analyzing FSM <FSM_1> for best encoding.Optimizing FSM <cpu/state> on signal <state[1:36]> with speed1 encoding.------------------------------------------------State | Encoding------------------------------------------------000001 | 000001000000000000000000000000000000000010 | 000000100000000000000000000000000000000011 | 100000000000000000000000000000000000000100 | 000100000000000000000000000000000000000101 | 000000000001000000000000000000000000000110 | 010000000000100000000000000000000000000111 | 010000001000000000000000000000000000001000 | 010000000000000001000000000000000000001001 | 010000000000000000010000000000000000001010 | 010000000000000000000100000000000000001011 | 010000000000000000000010000000000000001100 | 000010000000000000001000000000000000001101 | 010000000000000000000000000100000000001110 | 000000000100000000000000000000000000001111 | 000000000000010000000000000000000000010000 | 000000000000001000000000000000000000010001 | 000010000000000100000000000000000000010010 | 000000000010000000000000000000000000010011 | 000000000000000000000000000000000100010100 | 001010000000000000000000000000000000010101 | 010000000000000000000001000000000000010110 | 000000000000000000000000000001000000010111 | 000000000000000000000000000000000001011000 | 010000000000000000000000000010000000011001 | 000000000000000000000000000000010000011010 | 000000000000000000000000000000100000011011 | 000000000000000000000000000000001000011100 | 010000000000000000000000000000000010011101 | 000010000000000010000000000000000000011110 | 000010000000000000000000100000000000011111 | 0000100000000000000000000010000000000XXXXX | unreached100000 | 000010000000000000100000000000000000100001 | 000000000000000000000000010000000000100010 | 010000010000000000000000000000000000------------------------------------------------Analyzing FSM <FSM_0> for best encoding.Optimizing FSM <intc/state> on signal <state[1:2]> with gray encoding.-------------------State | Encoding-------------------0000 | 000001 | 010010 | 11-------------------Loading device for application Rf_Device from file '3s1000.nph' in environment C:\Xilinx.WARNING:Xst:2404 - FFs/Latches <curchr<7:7>> (without init value) have a constant value of 0 in block <chrmemmap>.WARNING:Xst:2404 - FFs/Latches <chrdatw<7:7>> (without init value) have a constant value of 0 in block <terminal>.WARNING:Xst:2404 - FFs/Latches <rowchr<7:7>> (without init value) have a constant value of 0 in block <terminal>.INFO:Xst:1651 - Address input of ROM <rom/Mrom__mux0000> is tied to register <cpu/addr>.INFO:Xst:1650 - The register is removed and the ROM is implemented as read-only block RAM.WARNING:Xst:1710 - FF/Latch <datai_0> (without init value) has a constant value of 0 in block <select>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <datai_1> (without init value) has a constant value of 0 in block <select>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <datai_2> (without init value) has a constant value of 0 in block <select>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <datai_3> (without init value) has a constant value of 0 in block <select>.INFO:Xst:2261 - The FF/Latch <rgb_r_0> in Unit <vga> is equivalent to the following 8 FFs/Latches, which will be removed : <rgb_r_1> <rgb_r_2> <rgb_r_3> <rgb_r_4> <rgb_r_5> <rgb_r_6> <rgb_r_7> <rgb_r_8>WARNING:Xst:1291 - FF/Latch <cmattri_5> is unconnected in block <terminal>.WARNING:Xst:1291 - FF/Latch <cmattri_6> is unconnected in block <terminal>.WARNING:Xst:1291 - FF/Latch <cmattri_7> is unconnected in block <terminal>.WARNING:Xst:1291 - FF/Latch <blank_r_3> is unconnected in block <vgai>.=========================================================================Advanced HDL Synthesis ReportMacro Statistics# FSMs : 4# RAMs : 51024x8-bit single-port block RAM : 1128x8-bit single-port block RAM : 11920x5-bit dual-port block RAM : 11920x8-bit dual-port distributed RAM : 11920x8-bit single-port block RAM : 1# ROMs : 32048x8-bit ROM : 14x1-bit ROM : 2# Multipliers : 29x6-bit multiplier : 19x8-bit multiplier : 1# Adders/Subtractors : 5610-bit subtractor : 111-bit adder : 511-bit adder carry out : 111-bit addsub : 113-bit adder : 116-bit adder : 716-bit addsub : 116-bit subtractor : 117-bit adder : 832-bit adder : 632-bit subtractor : 34-bit adder carry out : 25-bit adder : 15-bit subtractor : 16-bit adder : 16-bit subtractor : 28-bit adder : 18-bit adder carry out : 38-bit addsub : 39-bit adder : 39-bit subtractor : 4# Counters : 632-bit up counter : 14-bit up counter : 15-bit up counter : 27-bit up counter : 18-bit up counter : 1# Accumulators : 111-bit up accumulator : 1# Registers : 575Flip-Flops : 575# Latches : 126-bit latch : 48-bit latch : 8# Comparators : 3311-bit comparator equal : 111-bit comparator greatequal : 111-bit comparator greater : 111-bit comparator less : 512-bit comparator greater : 232-bit comparator greatequal : 14-bit comparator equal : 14-bit comparator greater : 25-bit comparator greatequal : 15-bit comparator less : 16-bit comparator equal : 47-bit comparator greatequal : 17-bit comparator less : 18-bit comparator greatequal : 48-bit comparator greater : 18-bit comparator less : 28-bit comparator lessequal : 4# Multiplexers : 321-bit 4-to-1 multiplexer : 171-bit 8-to-1 multiplexer : 316-bit 4-to-1 multiplexer : 13-bit 4-to-1 multiplexer : 48-bit 4-to-1 multiplexer : 48-bit 8-to-1 multiplexer : 3# Xors : 31-bit xor2 : 11-bit xor8 : 18-bit xor2 : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================WARNING:Xst:1988 - Unit <chrmemmap>: instances <Mcompar__cmp_ge0001>, <Mcompar__cmp_lt0000> of unit <LPM_COMPARE_5> and unit <LPM_COMPARE_7> are dual, second instance is removedWARNING:Xst:1988 - Unit <chrmemmap>: instances <Mcompar__cmp_ge0002>, <Mcompar__cmp_lt0001> of unit <LPM_COMPARE_6> and unit <LPM_COMPARE_8> are dual, second instance is removedWARNING:Xst:1989 - Unit <terminal>: instances <Mcompar__cmp_gt0000>, <Mcompar__cmp_gt0003> of unit <LPM_COMPARE_13> are equivalent, second instance is removedWARNING:Xst:1291 - FF/Latch <lincnt_0> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <lincnt_1> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <lincnt_2> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <lincnt_3> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <lincnt_4> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8421> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8401> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8411> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8431> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8441> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8451> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8461> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8471> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8481> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8491> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8501> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8511> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8521> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8531> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8541> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8551> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8561> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8571> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8581> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8591> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8601> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8611> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8621> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8631> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8641> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8651> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8661> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8671> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8681> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8691> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8701> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8711> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8721> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8731> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8741> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8751> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8761> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8771> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8781> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8791> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8801> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8811> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8821> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8831> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8841> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8851> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8861> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8871> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8881> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8891> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8901> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8911> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8921> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8931> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8941> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8951> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8961> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8971> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8981> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8991> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9001> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9011> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9021> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9051> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9031> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9041> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9061> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9071> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9081> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9091> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9101> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9111> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9121> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9131> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9141> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9151> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9161> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9171> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9181> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9191> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9201> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9211> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9221> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9231> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9241> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9251> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9261> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9271> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9281> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9291> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9301> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9311> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9321> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9331> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9361> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9341> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9351> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9371> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9381> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9391> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9401> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9411> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9421> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9431> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9441> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9451> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9461> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9471> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9481> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9491> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9501> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9511> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9521> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9531> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9541> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9551> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9561> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9571> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9581> is unconnected in block <chrmemmap>.WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9591> is unconnected in block <chrmemmap>.WARNING:Xst:1710 - FF/Latch <scnadr_0> (without init value) has a constant value of 0 in block <chrmemmap>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <scnadr_1> (without init value) has a constant value of 0 in block <chrmemmap>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <scnadr_2> (without init value) has a constant value of 0 in block <chrmemmap>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <scnadr_3> (without init value) has a constant value of 0 in block <chrmemmap>.WARNING:Xst:2040 - Unit testbench: 21 multi-source signals are replaced by logic (pull-up yes): adm3a/cmattr<0>, adm3a/cmattr<1>, adm3a/cmattr<2>, adm3a/cmattr<3>, adm3a/cmattr<4>, adm3a/cmdata<0>, adm3a/cmdata<1>, adm3a/cmdata<2>, adm3a/cmdata<3>, adm3a/cmdata<4>, adm3a/cmdata<5>, adm3a/cmdata<6>, adm3a/cmdata<7>, N185, N187, N189, N1911, N193, N195, N197, N199.WARNING:Xst:2042 - Unit chrmemmap: 13 internal tristates are replaced by logic (pull-up yes): attr<0>, attr<1>, attr<2>, attr<3>, attr<4>, data<0>, data<1>, data<2>, data<3>, data<4>, data<5>, data<6>, data<7>.Optimizing unit <testbench> ...Optimizing unit <alu> ...Optimizing unit <ps2_kbd> ...Optimizing unit <sync_2> ...Optimizing unit <sync_1> ...Optimizing unit <vga> ...Mapping all equations...WARNING:Xst:1291 - FF/Latch <adm3a/display/vgai/blank_r_3> is unconnected in block <testbench>.Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block testbench, actual ratio is 32.FlipFlop adm3a/cmaddr_0 has been replicated 5 time(s)FlipFlop adm3a/cmaddr_1 has been replicated 5 time(s)FlipFlop adm3a/cmaddr_2 has been replicated 5 time(s)FlipFlop adm3a/cmaddr_3 has been replicated 5 time(s)FlipFlop adm3a/display/chrcnt_0 has been replicated 1 time(s)FlipFlop adm3a/display/chrcnt_1 has been replicated 1 time(s)FlipFlop adm3a/display/chrcnt_2 has been replicated 1 time(s)FlipFlop adm3a/display/chrcnt_3 has been replicated 1 time(s)FlipFlop adm3a/vgai/sc_r_0 has been replicated 1 time(s)FlipFlop adm3a/vgai/sc_r_1 has been replicated 1 time(s)FlipFlop adm3a/vgai/sc_r_3 has been replicated 1 time(s)FlipFlop adm3a/vgai/sc_r_4 has been replicated 1 time(s)FlipFlop adm3a/vgai/sc_r_5 has been replicated 1 time(s)FlipFlop adm3a/vgai/sc_r_6 has been replicated 1 time(s)FlipFlop adm3a/vgai/sc_r_7 has been replicated 1 time(s)FlipFlop cpu/addr_0 has been replicated 1 time(s)FlipFlop cpu/addr_1 has been replicated 2 time(s)FlipFlop cpu/addr_2 has been replicated 2 time(s)FlipFlop cpu/addr_3 has been replicated 1 time(s)FlipFlop cpu/readio has been replicated 1 time(s)Final Macro Processing ...Processing Unit <testbench> :INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <adm3a/state_FFd7> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <cpu/state_FFd1> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <adm3a/vgai/sc_r_8> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <adm3a/vgai/ps2_clk_r_2> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <adm3a/display/vgai/blank_r_2> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.INFO:Xst:2387 - HDL ADVISOR - A 3-bit shift register was found for signal <adm3a/display/vgai/hsync_r_3> and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.Unit <testbench> processed.=========================================================================Final Register ReportMacro Statistics# Registers : 668Flip-Flops : 668==================================================================================================================================================* Partition Report *=========================================================================Partition Implementation Status-------------------------------No Partitions were found in this design.-------------------------------=========================================================================* Final Report *=========================================================================Final ResultsRTL Top Level Output File Name : testbench.ngrTop Level Output File Name : testbenchOutput Format : NGCOptimization Goal : SpeedKeep Hierarchy : NODesign Statistics# IOs : 54Cell Usage :# BELS : 6537# GND : 1# INV : 104# LUT1 : 233# LUT2 : 416# LUT2_D : 34# LUT2_L : 11# LUT3 : 1128# LUT3_D : 36# LUT3_L : 29# LUT4 : 2320# LUT4_D : 88# LUT4_L : 235# MULT_AND : 28# MUXCY : 662# MUXF5 : 609# MUXF6 : 175# MUXF7 : 59# MUXF8 : 23# VCC : 1# XORCY : 345# FlipFlops/Latches : 756# FD : 7# FDC : 23# FDCE : 62# FDE : 324# FDE_1 : 8# FDP : 6# FDPE : 21# FDR : 75# FDRE : 39# FDRE_1 : 42# FDRS : 47# FDRSE : 10# FDS : 3# FDSE : 1# LDCE : 56# LDE_1 : 32# RAMS : 844# RAM16X1D : 840# RAMB16_S9 : 3# RAMB16_S9_S9 : 1# Clock Buffers : 2# BUFGP : 2# IO Buffers : 52# IBUF : 2# IOBUF : 8# OBUF : 42# MULTs : 2# MULT18X18 : 2=========================================================================Device utilization summary:---------------------------Selected Device : 3s1000ft256-4Number of Slices: 2421 out of 7680 31%Number of Slice Flip Flops: 756 out of 15360 4%Number of 4 input LUTs: 6314 out of 15360 41%Number used as logic: 4634Number used as RAMs: 1680Number of IOs: 54Number of bonded IOBs: 54 out of 173 31%Number of BRAMs: 4 out of 24 16%Number of MULT18X18s: 2 out of 24 8%Number of GCLKs: 2 out of 8 25%=========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORTGENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------------------------+--------------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------------------------+--------------------------------+-------+clock | BUFGP | 1509 |reset_n | BUFGP | 32 |select1/selectd/_and0000(select1/selectd/_and00001:O)| NONE(*)(select1/selectd/mask_2)| 14 |select1/selectc/_and0000(select1/selectc/_and00001:O)| NONE(*)(select1/selectc/mask_2)| 14 |select1/selectb/_and0000(select1/selectb/_and00001:O)| NONE(*)(select1/selectb/comp_0)| 14 |select1/selecta/_and0000(select1/selecta/_and00001:O)| NONE(*)(select1/selecta/comp_2)| 14 |-----------------------------------------------------+--------------------------------+-------+(*) These 4 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.Asynchronous Control Signals Information:---------------------------------------------------------------------------+----------------------------------------------------+-------+Control Signal | Buffer(FF name) | Load |-----------------------------------+----------------------------------------------------+-------+reset(reset1_INV_0:O) | NONE(adm3a/display/vgai/gen_syncs_fit.vsync/sync_r)| 168 |-----------------------------------+----------------------------------------------------+-------+Timing Summary:---------------Speed Grade: -4Minimum period: 21.398ns (Maximum Frequency: 46.733MHz)Minimum input arrival time before clock: 8.800nsMaximum output required time after clock: 20.238nsMaximum combinational path delay: 7.342nsTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default period analysis for Clock 'clock'Clock period: 21.398ns (frequency: 46.733MHz)Total number of paths / destination ports: 244771 / 9411-------------------------------------------------------------------------Delay: 10.699ns (Levels of Logic = 6)Source: cpu/addr_10 (FF)Destination: intc/active_7 (FF)Source Clock: clock risingDestination Clock: clock fallingData Path: cpu/addr_10 to intc/active_7Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDE:C->Q 6 0.720 1.071 cpu/addr_10 (cpu/addr_10)LUT4:I2->O 1 0.551 0.000 select1/selectc/selectout1511 (N17364)MUXF5:I1->O 2 0.360 1.216 select1/selectc/selectout151_f5 (select1/selectc/selectout_map6043)LUT4_D:I0->O 1 0.551 0.827 select1/selectc/selectout169_1 (select1/selectc/selectout169)LUT4_D:I3->O 14 0.551 1.255 intc/_xor00151 (intc/_xor0015)LUT4_D:I2->O 7 0.551 1.092 intc/_not00161 (N2811)LUT4:I3->O 1 0.551 0.801 intc/_not0016 (intc/_not0016)FDRE_1:CE 0.602 intc/active_7----------------------------------------Total 10.699ns (4.437ns logic, 6.262ns route)(41.5% logic, 58.5% route)=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'clock'Total number of paths / destination ports: 633 / 633-------------------------------------------------------------------------Offset: 8.800ns (Levels of Logic = 2)Source: reset_n (PAD)Destination: cpu/readmem (FF)Destination Clock: clock risingData Path: reset_n to cpu/readmemGate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------BUFGP:I->O 240 0.401 3.045 reset_n_BUFGP (reset_n_BUFGP)INV:I->O 368 0.551 3.778 reset1_INV_0 (reset)FDRSE:R 1.026 cpu/writemem----------------------------------------Total 8.800ns (1.978ns logic, 6.822ns route)(22.5% logic, 77.5% route)=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectd/_and0000'Total number of paths / destination ports: 14 / 14-------------------------------------------------------------------------Offset: 2.474ns (Levels of Logic = 1)Source: data<6> (PAD)Destination: select1/selectd/mask_6 (LATCH)Destination Clock: select1/selectd/_and0000 fallingData Path: data<6> to select1/selectd/mask_6Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------IOBUF:IO->O 19 0.821 1.450 data_6_IOBUF (N15524)LDCE:D 0.203 select1/selectd/mask_6----------------------------------------Total 2.474ns (1.024ns logic, 1.450ns route)(41.4% logic, 58.6% route)=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectc/_and0000'Total number of paths / destination ports: 14 / 14-------------------------------------------------------------------------Offset: 2.474ns (Levels of Logic = 1)Source: data<6> (PAD)Destination: select1/selectc/mask_6 (LATCH)Destination Clock: select1/selectc/_and0000 fallingData Path: data<6> to select1/selectc/mask_6Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------IOBUF:IO->O 19 0.821 1.450 data_6_IOBUF (N15524)LDCE:D 0.203 select1/selectc/mask_6----------------------------------------Total 2.474ns (1.024ns logic, 1.450ns route)(41.4% logic, 58.6% route)=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectb/_and0000'Total number of paths / destination ports: 14 / 14-------------------------------------------------------------------------Offset: 2.474ns (Levels of Logic = 1)Source: data<6> (PAD)Destination: select1/selectb/mask_6 (LATCH)Destination Clock: select1/selectb/_and0000 fallingData Path: data<6> to select1/selectb/mask_6Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------IOBUF:IO->O 19 0.821 1.450 data_6_IOBUF (N15524)LDCE:D 0.203 select1/selectb/mask_6----------------------------------------Total 2.474ns (1.024ns logic, 1.450ns route)(41.4% logic, 58.6% route)=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selecta/_and0000'Total number of paths / destination ports: 14 / 14-------------------------------------------------------------------------Offset: 2.474ns (Levels of Logic = 1)Source: data<6> (PAD)Destination: select1/selecta/mask_6 (LATCH)Destination Clock: select1/selecta/_and0000 fallingData Path: data<6> to select1/selecta/mask_6Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------IOBUF:IO->O 19 0.821 1.450 data_6_IOBUF (N15524)LDCE:D 0.203 select1/selecta/mask_6----------------------------------------Total 2.474ns (1.024ns logic, 1.450ns route)(41.4% logic, 58.6% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'Total number of paths / destination ports: 2401 / 47-------------------------------------------------------------------------Offset: 20.238ns (Levels of Logic = 10)Source: cpu/addr_2 (FF)Destination: data<7> (PAD)Source Clock: clock risingData Path: cpu/addr_2 to data<7>Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDE:C->Q 29 0.720 2.031 cpu/addr_2 (cpu/addr_2)LUT4:I1->O 1 0.551 0.000 _and0000_inv168_SW01 (N17393)MUXF5:I1->O 2 0.360 0.903 _and0000_inv168_SW0_f5 (N16510)LUT4:I3->O 1 0.551 0.000 _and0000_inv1682 (N17396)MUXF5:I0->O 1 0.360 0.827 _and0000_inv168_f5 (_and0000_inv_map5607)LUT4:I3->O 9 0.551 1.192 _and0000_inv211 (_and0000_inv)LUT4:I2->O 1 0.551 1.140 N185LogicTrst120 (N185LogicTrst1_map5693)LUT4:I0->O 1 0.551 0.827 N185LogicTrst142_SW0 (N17018)LUT4:I3->O 16 0.551 1.576 N185LogicTrst142 (N256)LUT3:I0->O 1 0.551 0.801 N197LogicTrst115 (data_1_IOBUF)IOBUF:I->IO 5.644 data_1_IOBUF (data<1>)----------------------------------------Total 20.238ns (10.941ns logic, 9.297ns route)(54.1% logic, 45.9% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectc/_and0000'Total number of paths / destination ports: 552 / 8-------------------------------------------------------------------------Offset: 16.200ns (Levels of Logic = 7)Source: select1/selectc/mask_1 (LATCH)Destination: data<7> (PAD)Source Clock: select1/selectc/_and0000 fallingData Path: select1/selectc/mask_1 to data<7>Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------LDCE:G->Q 7 0.633 1.405 select1/selectc/mask_1 (select1/selectc/mask_1)LUT4:I0->O 1 0.551 0.000 select1/selectc/selectout1511 (N17364)MUXF5:I1->O 2 0.360 1.216 select1/selectc/selectout151_f5 (select1/selectc/selectout_map6043)LUT4_D:I0->LO 1 0.551 0.126 select1/selectc/selectout169_1 (N17618)LUT4:I3->O 17 0.551 1.684 intc/_not0027_SW0 (intc/_and0009)LUT4:I0->O 16 0.551 1.576 N185LogicTrst142 (N256)LUT3:I0->O 1 0.551 0.801 N197LogicTrst115 (data_1_IOBUF)IOBUF:I->IO 5.644 data_1_IOBUF (data<1>)----------------------------------------Total 16.200ns (9.392ns logic, 6.808ns route)(58.0% logic, 42.0% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectb/_and0000'Total number of paths / destination ports: 840 / 8-------------------------------------------------------------------------Offset: 17.126ns (Levels of Logic = 8)Source: select1/selectb/comp_1 (LATCH)Destination: data<7> (PAD)Source Clock: select1/selectb/_and0000 fallingData Path: select1/selectb/comp_1 to data<7>Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------LDCE:G->Q 3 0.633 1.246 select1/selectb/comp_1 (select1/selectb/comp_1)LUT4:I0->O 1 0.551 0.000 select1/select248_SW02 (N17390)MUXF5:I0->O 2 0.360 1.216 select1/select248_SW0_f5 (N16508)LUT4:I0->O 1 0.551 0.000 select1/select2482 (N17392)MUXF5:I0->O 2 0.360 1.216 select1/select248_f5 (select1/select2_map5499)LUT4:I0->O 9 0.551 1.319 ram/_and0000_inv1 (ram/_and0000_inv)LUT4:I1->O 16 0.551 1.576 N185LogicTrst142 (N256)LUT3:I0->O 1 0.551 0.801 N197LogicTrst115 (data_1_IOBUF)IOBUF:I->IO 5.644 data_1_IOBUF (data<1>)----------------------------------------Total 17.126ns (9.752ns logic, 7.374ns route)(56.9% logic, 43.1% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selecta/_and0000'Total number of paths / destination ports: 840 / 8-------------------------------------------------------------------------Offset: 19.715ns (Levels of Logic = 9)Source: select1/selecta/mask_1 (LATCH)Destination: data<7> (PAD)Source Clock: select1/selecta/_and0000 fallingData Path: select1/selecta/mask_1 to data<7>Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------LDCE:G->Q 7 0.633 1.405 select1/selecta/mask_1 (select1/selecta/mask_1)LUT4:I0->O 1 0.551 0.000 _and0000_inv181 (N17350)MUXF5:I1->O 1 0.360 1.140 _and0000_inv18_f5 (_and0000_inv_map5561)LUT4:I0->O 1 0.551 1.140 _and0000_inv108 (_and0000_inv_map5588)LUT4:I0->O 9 0.551 1.192 _and0000_inv211 (_and0000_inv)LUT4:I2->O 1 0.551 1.140 N185LogicTrst120 (N185LogicTrst1_map5693)LUT4:I0->O 1 0.551 0.827 N185LogicTrst142_SW0 (N17018)LUT4:I3->O 16 0.551 1.576 N185LogicTrst142 (N256)LUT3:I0->O 1 0.551 0.801 N197LogicTrst115 (data_1_IOBUF)IOBUF:I->IO 5.644 data_1_IOBUF (data<1>)----------------------------------------Total 19.715ns (10.494ns logic, 9.221ns route)(53.2% logic, 46.8% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectd/_and0000'Total number of paths / destination ports: 624 / 8-------------------------------------------------------------------------Offset: 17.403ns (Levels of Logic = 8)Source: select1/selectd/mask_1 (LATCH)Destination: data<7> (PAD)Source Clock: select1/selectd/_and0000 fallingData Path: select1/selectd/mask_1 to data<7>Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------LDCE:G->Q 7 0.633 1.405 select1/selectd/mask_1 (select1/selectd/mask_1)LUT4:I0->O 1 0.551 0.000 select1/selectd/selectout791 (N17330)MUXF5:I1->O 1 0.360 1.140 select1/selectd/selectout79_f5 (select1/selectd/selectout_map5389)LUT4_D:I0->O 8 0.551 1.278 select1/selectd/selectout169 (select1/selectd/selectout_map5416)LUT4:I1->O 1 0.551 0.827 N187LogicTrst127_SW0_SW0 (N17028)LUT4:I3->O 1 0.551 1.140 N187LogicTrst127_SW0 (N16922)LUT4:I0->O 1 0.551 0.869 N187LogicTrst127 (N187LogicTrst_map5838)LUT3:I2->O 1 0.551 0.801 N187LogicTrst134 (data_6_IOBUF)IOBUF:I->IO 5.644 data_6_IOBUF (data<6>)----------------------------------------Total 17.403ns (9.943ns logic, 7.460ns route)(57.1% logic, 42.9% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'reset_n'Total number of paths / destination ports: 32 / 8-------------------------------------------------------------------------Offset: 15.912ns (Levels of Logic = 7)Source: select1/selectb/datai_3 (LATCH)Destination: data<3> (PAD)Source Clock: reset_n fallingData Path: select1/selectb/datai_3 to data<3>Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------LDE_1:G->Q 1 0.633 0.869 select1/selectb/datai_3 (select1/selectb/datai_3)LUT4:I2->O 1 0.551 0.996 N193LogicTrst26 (N193LogicTrst_map5708)LUT4:I1->O 1 0.551 0.827 N193LogicTrst34 (N193LogicTrst_map5710)LUT4:I3->O 1 0.551 0.827 N193LogicTrst61 (N193LogicTrst_map5716)LUT4:I3->O 1 0.551 1.140 N193LogicTrst97_SW0 (N16914)LUT4:I0->O 1 0.551 0.869 N193LogicTrst97 (N193LogicTrst_map5723)LUT3:I2->O 1 0.551 0.801 N193LogicTrst110 (data_3_IOBUF)IOBUF:I->IO 5.644 data_3_IOBUF (data<3>)----------------------------------------Total 15.912ns (9.583ns logic, 6.329ns route)(60.2% logic, 39.8% route)=========================================================================Timing constraint: Default path analysisTotal number of paths / destination ports: 2 / 2-------------------------------------------------------------------------Delay: 7.342ns (Levels of Logic = 2)Source: ps2_data (PAD)Destination: diag<4> (PAD)Data Path: ps2_data to diag<4>Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------IBUF:I->O 2 0.821 0.877 ps2_data_IBUF (ps2_data_IBUF)OBUF:I->O 5.644 diag_4_OBUF (diag<4>)----------------------------------------Total 7.342ns (6.465ns logic, 0.877ns route)(88.1% logic, 11.9% route)=========================================================================CPU : 204.47 / 204.97 s | Elapsed : 205.00 / 205.00 s-->Total memory usage is 239120 kilobytesNumber of errors : 0 ( 0 filtered)Number of warnings : 162 ( 0 filtered)Number of infos : 14 ( 0 filtered)
Go to most recent revision | Compare with Previous | Blame | View Log