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Release 8.2.02i - xst I.33
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.50 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.50 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: testbench.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "testbench.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "testbench"
Output Format                      : NGC
Target Device                      : xc3s1000-4-ft256

---- Source Options
Top Module Name                    : testbench
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : testbench.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/common.vhd" in Library work.
Architecture common of Entity common is up to date.
Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/ps2_kbd.vhd" in Library work.
Architecture arch of Entity ps2_kbd is up to date.
Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/vga.vhd" in Library work.
Architecture vga_arch of Entity vga is up to date.
Architecture sync_arch of Entity sync is up to date.
Compiling verilog file "vgachr.v" in library work
Module <terminal> compiled
Module <chrmemmap> compiled
Module <chrrom> compiled
Module <scnrom> compiled
Compiling verilog file "cpu8080.v" in library work
Module <scnromu> compiled
Module <cpu8080> compiled
Compiling verilog file "testbench.v" in library work
Module <alu> compiled
Module <testbench> compiled
Module <select> compiled
Module <selectone> compiled
Module <intcontrol> compiled
Compiling verilog include file "test.rom"
Module <rom> compiled
Module <ram> compiled
No errors in compilation
Analysis of file <"testbench.prj"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for module <testbench> in library <work>.

Analyzing hierarchy for module <select> in library <work>.

Analyzing hierarchy for module <cpu8080> in library <work>.

Analyzing hierarchy for module <rom> in library <work>.

Analyzing hierarchy for module <ram> in library <work>.

Analyzing hierarchy for module <intcontrol> in library <work>.

Analyzing hierarchy for module <terminal> in library <work>.

Analyzing hierarchy for module <selectone> in library <work>.

Analyzing hierarchy for module <alu> in library <work>.

Analyzing hierarchy for module <chrmemmap> in library <work>.

Analyzing hierarchy for entity <ps2_kbd> in library <work> (architecture <arch>) with generics.
        FREQ = 50000

Analyzing hierarchy for module <scnrom> in library <work>.

Analyzing hierarchy for module <scnromu> in library <work>.

Analyzing hierarchy for entity <vga> in library <work> (architecture <vga_arch>) with generics.
        CLK_DIV = 2
        FIT_TO_SCREEN = true
        FREQ = 50000
        LINES_PER_FRAME = 480
        NUM_RGB_BITS = 3
        PIXEL_WIDTH = 1
        PIXELS_PER_LINE = 640

Analyzing hierarchy for module <chrrom> in library <work>.

Analyzing hierarchy for entity <sync> in library <work> (architecture <sync_arch>) with generics.
        FREQ = 25000
        PERIOD = 32
        START = 26
        VISIBLE = 640
        WIDTH = 4

Analyzing hierarchy for entity <sync> in library <work> (architecture <sync_arch>) with generics.
        FREQ = 31
        PERIOD = 16784
        START = 15700
        VISIBLE = 480
        WIDTH = 64

Building hierarchy successfully finished.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <testbench>.
Module <testbench> is correct for synthesis.
 
Analyzing module <select> in library <work>.
Module <select> is correct for synthesis.
 
Analyzing module <selectone> in library <work>.
Module <selectone> is correct for synthesis.
 
Analyzing module <cpu8080> in library <work>.
Module <cpu8080> is correct for synthesis.
 
Analyzing module <alu> in library <work>.
Module <alu> is correct for synthesis.
 
Analyzing module <rom> in library <work>.
Module <rom> is correct for synthesis.
 
Analyzing module <ram> in library <work>.
Module <ram> is correct for synthesis.
 
Analyzing module <intcontrol> in library <work>.
Module <intcontrol> is correct for synthesis.
 
Analyzing module <terminal> in library <work>.
Module <terminal> is correct for synthesis.
 
Analyzing module <chrmemmap> in library <work>.
Module <chrmemmap> is correct for synthesis.
 
Analyzing generic Entity <vga> in library <work> (Architecture <vga_arch>).
        PIXEL_WIDTH = 1
        PIXELS_PER_LINE = 640
        CLK_DIV = 2
        FIT_TO_SCREEN = true
        FREQ = 50000
        LINES_PER_FRAME = 480
        NUM_RGB_BITS = 3
Entity <vga> analyzed. Unit <vga> generated.

Analyzing generic Entity <sync.1> in library <work> (Architecture <sync_arch>).
        FREQ = 25000
        VISIBLE = 640
        WIDTH = 4
        PERIOD = 32
        START = 26
Entity <sync.1> analyzed. Unit <sync.1> generated.

Analyzing generic Entity <sync.2> in library <work> (Architecture <sync_arch>).
        FREQ = 31
        PERIOD = 16784
        START = 15700
        VISIBLE = 480
        WIDTH = 64
Entity <sync.2> analyzed. Unit <sync.2> generated.

Analyzing module <chrrom> in library <work>.
Module <chrrom> is correct for synthesis.
 
Analyzing generic Entity <ps2_kbd> in library <work> (Architecture <arch>).
        FREQ = 50000
Entity <ps2_kbd> analyzed. Unit <ps2_kbd> generated.

Analyzing module <scnrom> in library <work>.
Module <scnrom> is correct for synthesis.
 
Analyzing module <scnromu> in library <work>.
Module <scnromu> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <rom>.
    Related source file is "testbench.v".
    Found 2048x8-bit ROM for signal <datao>.
    Found 8-bit tristate buffer for signal <data>.
    Summary:
        inferred   1 ROM(s).
        inferred   8 Tristate(s).
Unit <rom> synthesized.


Synthesizing Unit <ram>.
    Related source file is "testbench.v".
    Found 1024x8-bit single-port block RAM for signal <ramcore>.
    -----------------------------------------------------------------------
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 1024-word x 8-bit                   |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <clock>         | fall     |
    |     enA            | connected to signal <select>        | high     |
    |     weA            | connected to signal <write>         | high     |
    |     addrA          | connected to signal <addr>          |          |
    |     diA            | connected to signal <data>          |          |
    |     doA            | connected to signal <datao>         |          |
    -----------------------------------------------------------------------
    Found 8-bit tristate buffer for signal <data>.
    Summary:
        inferred   1 RAM(s).
        inferred   8 Tristate(s).
Unit <ram> synthesized.


Synthesizing Unit <intcontrol>.
    Related source file is "testbench.v".
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 3                                              |
    | Inputs             | 0                                              |
    | Outputs            | 4                                              |
    | Clock              | clock (falling_edge)                           |
    | Clock enable       | $not0004 (positive)                            |
    | Reset              | reset (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit tristate buffer for signal <data>.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0000>.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0001>.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0002>.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0003>.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0004>.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0005>.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0006>.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0007>.
    Found 8-bit register for signal <active>.
    Found 8-bit register for signal <datai>.
    Found 8-bit register for signal <edges>.
    Found 8-bit register for signal <mask>.
    Found 8-bit register for signal <polarity>.
    Found 8-bit register for signal <vbase>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred  48 D-type flip-flop(s).
        inferred   8 Multiplexer(s).
        inferred   8 Tristate(s).
Unit <intcontrol> synthesized.


Synthesizing Unit <selectone>.
    Related source file is "testbench.v".
WARNING:Xst:647 - Input <addr<9:8>> is never used.
WARNING:Xst:647 - Input <addr<1>> is never used.
WARNING:Xst:737 - Found 6-bit latch for signal <comp>.
WARNING:Xst:737 - Found 8-bit latch for signal <mask>.
WARNING:Xst:737 - Found 8-bit latch for signal <datai>.
    Found 8-bit tristate buffer for signal <data>.
    Found 6-bit comparator equal for signal <$cmp_eq0000> created at line 291.
    Summary:
        inferred   1 Comparator(s).
        inferred   8 Tristate(s).
Unit <selectone> synthesized.


Synthesizing Unit <alu>.
    Related source file is "cpu8080.v".
WARNING:Xst:646 - Signal <resi> is assigned but never used.
    Found 1-bit 8-to-1 multiplexer for signal <cout>.
    Found 1-bit 8-to-1 multiplexer for signal <auxcar>.
    Found 5-bit adder for signal <$add0001> created at line 1578.
    Found 8-bit adder carry out for signal <$addsub0000> created at line 1571.
    Found 4-bit adder carry out for signal <$addsub0001> created at line 1572.
    Found 6-bit subtractor for signal <$sub0000> created at line 1584.
    Found 6-bit subtractor for signal <$sub0001> created at line 1590.
    Found 9-bit subtractor for signal <$sub0002> created at line 1583.
    Found 8-bit xor2 for signal <$xor0000> created at line 1601.
    Found 1-bit xor8 for signal <$xor0002>.
    Summary:
        inferred   8 Adder/Subtractor(s).
        inferred  10 Multiplexer(s).
        inferred   1 Xor(s).
Unit <alu> synthesized.


Synthesizing Unit <ps2_kbd>.
    Related source file is "C:/Xilinx/ISEexamples/cpu8080/ps2_kbd.vhd".
WARNING:Xst:646 - Signal <keyrel_r> is assigned but never used.
    Found 13-bit adder for signal <$addsub0000> created at line 112.
    Found 4-bit up counter for signal <bitcnt_r>.
    Found 1-bit register for signal <error_r>.
    Found 5-bit register for signal <ps2_clk_r>.
    Found 1-bit register for signal <rdy_r>.
    Found 10-bit register for signal <sc_r>.
    Found 13-bit register for signal <timer_r>.
    Summary:
        inferred   1 Counter(s).
        inferred  30 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
Unit <ps2_kbd> synthesized.


Synthesizing Unit <scnrom>.
    Related source file is "vgachr.v".
Unit <scnrom> synthesized.


Synthesizing Unit <scnromu>.
    Related source file is "vgachr.v".
Unit <scnromu> synthesized.


Synthesizing Unit <chrrom>.
    Related source file is "vgachr.v".
    Found 2048x8-bit ROM for signal <data>.
    Summary:
        inferred   1 ROM(s).
Unit <chrrom> synthesized.


Synthesizing Unit <sync_1>.
    Related source file is "C:/Xilinx/ISEexamples/cpu8080/vga.vhd".
    Found 16-bit adder for signal <$addsub0000> created at line 398.
    Found 1-bit register for signal <blank_r>.
    Found 16-bit register for signal <cnt_r>.
    Found 1-bit register for signal <gate_r>.
    Found 1-bit register for signal <sync_r>.
    Summary:
        inferred   3 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
Unit <sync_1> synthesized.


Synthesizing Unit <sync_2>.
    Related source file is "C:/Xilinx/ISEexamples/cpu8080/vga.vhd".
    Found 16-bit adder for signal <$addsub0000> created at line 398.
    Found 1-bit register for signal <blank_r>.
    Found 16-bit register for signal <cnt_r>.
    Found 1-bit register for signal <gate_r>.
    Found 1-bit register for signal <sync_r>.
    Summary:
        inferred   3 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
Unit <sync_2> synthesized.


Synthesizing Unit <select>.
    Related source file is "testbench.v".
    Found 1-bit register for signal <bootstrap>.
    Found 8-bit tristate buffer for signal <data>.
    Found 8-bit register for signal <datai>.
    Found 4-bit comparator equal for signal <selacc>.
    Found 4-bit register for signal <seladr>.
    Summary:
        inferred  13 D-type flip-flop(s).
        inferred   1 Comparator(s).
        inferred   8 Tristate(s).
Unit <select> synthesized.


Synthesizing Unit <cpu8080>.
    Related source file is "cpu8080.v".
INFO:Xst:1799 - State 0XXXXX is never reached in FSM <state>.
    Found finite state machine <FSM_1> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 39                                             |
    | Transitions        | 1171                                           |
    | Inputs             | 148                                            |
    | Outputs            | 38                                             |
    | Clock              | clock (rising_edge)                            |
    | Reset              | reset (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4x16-bit ROM for signal <$mux0041> created at line 268.
    Found 16-bit register for signal <addr>.
    Found 1-bit register for signal <writeio>.
    Found 1-bit register for signal <readio>.
    Found 1-bit register for signal <writemem>.
    Found 1-bit register for signal <readmem>.
    Found 1-bit register for signal <inta>.
    Found 8-bit tristate buffer for signal <data>.
    Found 32-bit adder for signal <$add0000> created at line 501.
    Found 32-bit adder for signal <$add0001> created at line 513.
    Found 32-bit adder for signal <$add0002> created at line 525.
    Found 16-bit adder for signal <$add0003> created at line 980.
    Found 16-bit adder for signal <$add0004> created at line 895.
    Found 32-bit adder for signal <$add0005> created at line 570.
    Found 32-bit adder for signal <$add0006> created at line 558.
    Found 32-bit adder for signal <$add0007> created at line 546.
    Found 17-bit adder for signal <$add0008> created at line 491.
    Found 17-bit adder for signal <$addsub0000>.
    Found 17-bit adder for signal <$addsub0001>.
    Found 17-bit adder for signal <$addsub0002>.
    Found 8-bit adder for signal <$addsub0003>.
    Found 8-bit addsub for signal <$addsub0004>.
    Found 8-bit addsub for signal <$addsub0005>.
    Found 8-bit addsub for signal <$addsub0006>.
    Found 16-bit adder for signal <$addsub0007> created at line 1092.
    Found 6-bit adder for signal <$addsub0008>.
    Found 16-bit adder for signal <$addsub0009> created at line 1051.
    Found 8-bit adder carry out for signal <$addsub0010>.
    Found 8-bit adder carry out for signal <$addsub0011>.
    Found 4-bit comparator greater for signal <$cmp_gt0000> created at line 1373.
    Found 4-bit comparator greater for signal <$cmp_gt0001> created at line 361.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0025> created at line 317.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0031> created at line 317.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0044> created at line 321.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0045>.
    Found 16-bit adder for signal <$share0000> created at line 317.
    Found 16-bit addsub for signal <$share0006> created at line 268.
    Found 32-bit subtractor for signal <$sub0000> created at line 546.
    Found 32-bit subtractor for signal <$sub0001> created at line 558.
    Found 32-bit subtractor for signal <$sub0002> created at line 570.
    Found 16-bit subtractor for signal <$sub0003> created at line 766.
    Found 1-bit register for signal <alucin>.
    Found 8-bit register for signal <aluopra>.
    Found 8-bit register for signal <aluoprb>.
    Found 3-bit register for signal <alusel>.
    Found 1-bit register for signal <auxcar>.
    Found 1-bit register for signal <carry>.
    Found 1-bit register for signal <dataeno>.
    Found 8-bit register for signal <datao>.
    Found 1-bit register for signal <ei>.
    Found 1-bit register for signal <eienb>.
    Found 1-bit register for signal <intcyc>.
    Found 8-bit register for signal <opcode>.
    Found 1-bit register for signal <parity>.
    Found 16-bit register for signal <pc>.
    Found 2-bit register for signal <popdes>.
    Found 16-bit register for signal <raddrhold>.
    Found 8-bit register for signal <rdatahold>.
    Found 8-bit register for signal <rdatahold2>.
    Found 3-bit register for signal <regd>.
    Found 64-bit register for signal <regfil>.
    Found 1-bit register for signal <sign>.
    Found 16-bit register for signal <sp>.
    Found 6-bit register for signal <statesel>.
    Found 16-bit register for signal <waddrhold>.
    Found 8-bit register for signal <wdatahold>.
    Found 8-bit register for signal <wdatahold2>.
    Found 1-bit register for signal <zero>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred   1 ROM(s).
        inferred 237 D-type flip-flop(s).
        inferred  33 Adder/Subtractor(s).
        inferred   2 Comparator(s).
        inferred  38 Multiplexer(s).
        inferred   8 Tristate(s).
Unit <cpu8080> synthesized.


Synthesizing Unit <vga>.
    Related source file is "C:/Xilinx/ISEexamples/cpu8080/vga.vhd".
WARNING:Xst:646 - Signal <line_cnt> is assigned but never used.
WARNING:Xst:646 - Signal <pixel_cnt<15:4>> is assigned but never used.
    Found 3-bit register for signal <blank_r>.
    Found 1-bit register for signal <cke>.
    Found 8-bit up counter for signal <clk_div_cnt>.
    Found 1-bit register for signal <eof_r>.
    Found 3-bit register for signal <hsync_r>.
    Found 16-bit register for signal <pixel_data_r>.
    Found 1-bit register for signal <rd_r>.
    Found 9-bit register for signal <rgb_r>.
    Summary:
        inferred   1 Counter(s).
        inferred  34 D-type flip-flop(s).
Unit <vga> synthesized.


Synthesizing Unit <chrmemmap>.
    Related source file is "vgachr.v".
WARNING:Xst:646 - Signal <curatr<4>> is assigned but never used.
WARNING:Xst:646 - Signal <blank> is assigned but never used.
    Found 1920x8-bit single-port block RAM for signal <scnbuf>.
    -----------------------------------------------------------------------
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 1920-word x 8-bit                   |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <clk>           | rise     |
    |     weA            | connected to signal <write>         | high     |
    |     addrA          | connected to signal <addr>          |          |
    |     diA            | connected to signal <data>          |          |
    |     doA            | connected to signal <datao>         |          |
    -----------------------------------------------------------------------
    Found 1920x8-bit dual-port distributed RAM for signal <scnbuf>.
    -----------------------------------------------------------------------
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 1920-word x 8-bit                   |          |
    |     clkA           | connected to signal <clk>           | rise     |
    |     weA            | connected to signal <write>         | high     |
    |     addrA          | connected to signal <addr>          |          |
    |     diA            | connected to signal <data>          |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 1920-word x 8-bit                   |          |
    |     addrB          | connected to internal node          |          |
    |     doB            | connected to internal node          |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 1920x5-bit dual-port block RAM for signal <atrbuf>.
    -----------------------------------------------------------------------
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 1920-word x 5-bit                   |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <clk>           | rise     |
    |     weA            | connected to signal <write>         | high     |
    |     addrA          | connected to signal <addr>          |          |
    |     diA            | connected to signal <attr>          |          |
    |     doA            | connected to signal <attro>         |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 1920-word x 5-bit                   |          |
    |     mode           | read-first                          |          |
    |     clkB           | connected to signal <clk>           | rise     |
    |     addrB          | connected to internal node          |          |
    |     doB            | connected to signal <curatr>        |          |
    -----------------------------------------------------------------------
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <fchsta> of Case statement line 873 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
        - add an 'INIT' attribute on signal <fchsta> (optimization is then done without any risk)
        - use the attribute 'signal_encoding user' to avoid onehot optimization
        - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Found finite state machine <FSM_2> for signal <fchsta>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 7                                              |
    | Inputs             | 1                                              |
    | Outputs            | 6                                              |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $not0008 (positive)                            |
    | Reset              | rst (positive)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:643 - "vgachr.v" line 945: The result of a 9x6-bit multiplication is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit tristate buffer for signal <attr>.
    Found 8-bit tristate buffer for signal <data>.
    Found 11-bit adder for signal <$add0000> created at line 928.
    Found 9-bit subtractor for signal <$addsub0000> created at line 945.
    Found 11-bit adder for signal <$addsub0001> created at line 945.
    Found 11-bit comparator equal for signal <$cmp_eq0003> created at line 882.
    Found 32-bit comparator greatequal for signal <$cmp_ge0000> created at line 814.
    Found 7-bit comparator greatequal for signal <$cmp_ge0001> created at line 854.
    Found 5-bit comparator greatequal for signal <$cmp_ge0002> created at line 858.
    Found 7-bit comparator less for signal <$cmp_lt0000> created at line 854.
    Found 5-bit comparator less for signal <$cmp_lt0001> created at line 858.
    Found 8-bit comparator less for signal <$cmp_lt0002> created at line 945.
    Found 9x6-bit multiplier for signal <$mult0002> created at line 945.
    Found 16-bit 4-to-1 multiplexer for signal <$mux0000> created at line 911.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0001> created at line 904.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0002> created at line 904.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0003> created at line 904.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0004> created at line 904.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0005> created at line 904.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0006> created at line 904.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0007> created at line 904.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0008> created at line 904.
    Found 8-bit 4-to-1 multiplexer for signal <$mux0009> created at line 883.
    Found 1-bit xor2 for signal <$xor0000> created at line 903.
    Found 32-bit up counter for signal <blinkcnt>.
    Found 1-bit register for signal <blon>.
    Found 7-bit up counter for signal <chrcnt>.
    Found 8-bit register for signal <curchr>.
    Found 5-bit up counter for signal <lincnt>.
    Found 8-bit register for signal <pixdatl>.
    Found 16-bit register for signal <pixeldata>.
    Found 5-bit up counter for signal <rowcnt>.
    Found 11-bit up accumulator for signal <scnadr>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred   3 RAM(s).
        inferred   4 Counter(s).
        inferred   1 Accumulator(s).
        inferred  33 D-type flip-flop(s).
        inferred   3 Adder/Subtractor(s).
        inferred   1 Multiplier(s).
        inferred   7 Comparator(s).
        inferred  32 Multiplexer(s).
        inferred  13 Tristate(s).
Unit <chrmemmap> synthesized.


Synthesizing Unit <terminal>.
    Related source file is "vgachr.v".
WARNING:Xst:646 - Signal <parity> is assigned but never used.
WARNING:Xst:646 - Signal <cmattri<7:5>> is assigned but never used.
WARNING:Xst:646 - Signal <error> is assigned but never used.
    Register <cmattre> equivalent to <cmdatae> has been removed
    Found finite state machine <FSM_3> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 20                                             |
    | Transitions        | 88                                             |
    | Inputs             | 21                                             |
    | Outputs            | 21                                             |
    | Clock              | clock (rising_edge)                            |
    | Reset              | reset (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 00100                                          |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:643 - "vgachr.v" line 688: The result of a 9x8-bit multiplication is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 4x1-bit ROM for signal <$mux0023> created at line 372.
    Found 8-bit tristate buffer for signal <data>.
    Found 11-bit adder for signal <$add0002> created at line 558.
    Found 9-bit subtractor for signal <$addsub0000> created at line 688.
    Found 11-bit adder for signal <$addsub0001> created at line 521.
    Found 11-bit adder for signal <$addsub0002>.
    Found 11-bit adder carry out for signal <$addsub0003> created at line 541.
    Found 8-bit comparator greatequal for signal <$cmp_ge0000> created at line 384.
    Found 11-bit comparator greatequal for signal <$cmp_ge0001> created at line 413.
    Found 8-bit comparator greatequal for signal <$cmp_ge0002> created at line 685.
    Found 8-bit comparator greatequal for signal <$cmp_ge0003> created at line 358.
    Found 8-bit comparator greatequal for signal <$cmp_ge0004> created at line 361.
    Found 12-bit comparator greater for signal <$cmp_gt0000> created at line 541.
    Found 8-bit comparator greater for signal <$cmp_gt0001> created at line 707.
    Found 11-bit comparator greater for signal <$cmp_gt0002> created at line 425.
    Found 12-bit comparator greater for signal <$cmp_gt0003> created at line 541.
    Found 8-bit comparator lessequal for signal <$cmp_le0000> created at line 685.
    Found 8-bit comparator lessequal for signal <$cmp_le0001> created at line 685.
    Found 8-bit comparator lessequal for signal <$cmp_le0002> created at line 358.
    Found 8-bit comparator lessequal for signal <$cmp_le0003> created at line 361.
    Found 11-bit comparator less for signal <$cmp_lt0000> created at line 398.
    Found 11-bit comparator less for signal <$cmp_lt0001> created at line 519.
    Found 11-bit comparator less for signal <$cmp_lt0002> created at line 555.
    Found 11-bit comparator less for signal <$cmp_lt0003> created at line 603.
    Found 8-bit comparator less for signal <$cmp_lt0004> created at line 707.
    Found 11-bit comparator less for signal <$cmp_lt0005> created at line 432.
    Found 9x8-bit multiplier for signal <$mult0002> created at line 688.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0005>.
    Found 1-bit 8-to-1 multiplexer for signal <$mux0007>.
    Found 11-bit addsub for signal <$share0000> created at line 372.
    Found 10-bit subtractor for signal <$sub0000> created at line 688.
    Found 5-bit subtractor for signal <$sub0001> created at line 708.
    Found 1-bit register for signal <capslock>.
    Found 8-bit register for signal <chrdatw>.
    Found 1-bit register for signal <clrrdy>.
    Found 11-bit register for signal <cmaddr>.
    Found 5-bit tristate buffer for signal <cmattr>.
    Found 8-bit register for signal <cmattri>.
    Found 8-bit tristate buffer for signal <cmdata>.
    Found 1-bit register for signal <cmdatae>.
    Found 8-bit register for signal <cmdatai>.
    Found 1-bit register for signal <cmread>.
    Found 1-bit register for signal <cmwrite>.
    Found 5-bit register for signal <curatr>.
    Found 11-bit register for signal <cursor>.
    Found 8-bit register for signal <datao>.
    Found 1-bit register for signal <extcod>.
    Found 1-bit register for signal <extkey>.
    Found 1-bit register for signal <leftctrl>.
    Found 1-bit register for signal <leftshift>.
    Found 1-bit register for signal <outrdy>.
    Found 1-bit register for signal <relcod>.
    Found 1-bit register for signal <rightctrl>.
    Found 1-bit register for signal <rightshift>.
    Found 8-bit register for signal <rowchr>.
    Found 1-bit register for signal <scnrdy>.
    Found 11-bit register for signal <tcursor>.
    Found 1-bit register for signal <wrtchr>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred   1 ROM(s).
        inferred  93 D-type flip-flop(s).
        inferred   8 Adder/Subtractor(s).
        inferred   1 Multiplier(s).
        inferred  19 Comparator(s).
        inferred   2 Multiplexer(s).
        inferred  21 Tristate(s).
Unit <terminal> synthesized.


Synthesizing Unit <testbench>.
    Related source file is "testbench.v".
Unit <testbench> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 4
 1024x8-bit single-port block RAM                      : 1
 1920x5-bit dual-port block RAM                        : 1
 1920x8-bit dual-port distributed RAM                  : 1
 1920x8-bit single-port block RAM                      : 1
# ROMs                                                 : 4
 2048x8-bit ROM                                        : 2
 4x1-bit ROM                                           : 1
 4x16-bit ROM                                          : 1
# Multipliers                                          : 2
 9x6-bit multiplier                                    : 1
 9x8-bit multiplier                                    : 1
# Adders/Subtractors                                   : 55
 10-bit subtractor                                     : 1
 11-bit adder                                          : 5
 11-bit adder carry out                                : 1
 11-bit addsub                                         : 1
 13-bit adder                                          : 1
 16-bit adder                                          : 7
 16-bit addsub                                         : 1
 16-bit subtractor                                     : 1
 17-bit adder                                          : 8
 32-bit adder                                          : 6
 32-bit subtractor                                     : 3
 4-bit adder carry out                                 : 1
 5-bit adder                                           : 1
 5-bit subtractor                                      : 1
 6-bit adder                                           : 1
 6-bit subtractor                                      : 2
 8-bit adder                                           : 1
 8-bit adder carry out                                 : 3
 8-bit addsub                                          : 3
 9-bit adder                                           : 3
 9-bit subtractor                                      : 4
# Counters                                             : 6
 32-bit up counter                                     : 1
 4-bit up counter                                      : 1
 5-bit up counter                                      : 2
 7-bit up counter                                      : 1
 8-bit up counter                                      : 1
# Accumulators                                         : 1
 11-bit up accumulator                                 : 1
# Registers                                            : 104
 1-bit register                                        : 51
 10-bit register                                       : 1
 11-bit register                                       : 3
 13-bit register                                       : 1
 16-bit register                                       : 9
 2-bit register                                        : 1
 3-bit register                                        : 4
 4-bit register                                        : 1
 5-bit register                                        : 2
 6-bit register                                        : 1
 8-bit register                                        : 29
 9-bit register                                        : 1
# Latches                                              : 12
 6-bit latch                                           : 4
 8-bit latch                                           : 8
# Comparators                                          : 33
 11-bit comparator equal                               : 1
 11-bit comparator greatequal                          : 1
 11-bit comparator greater                             : 1
 11-bit comparator less                                : 5
 12-bit comparator greater                             : 2
 32-bit comparator greatequal                          : 1
 4-bit comparator equal                                : 1
 4-bit comparator greater                              : 2
 5-bit comparator greatequal                           : 1
 5-bit comparator less                                 : 1
 6-bit comparator equal                                : 4
 7-bit comparator greatequal                           : 1
 7-bit comparator less                                 : 1
 8-bit comparator greatequal                           : 4
 8-bit comparator greater                              : 1
 8-bit comparator less                                 : 2
 8-bit comparator lessequal                            : 4
# Multiplexers                                         : 29
 1-bit 4-to-1 multiplexer                              : 17
 1-bit 8-to-1 multiplexer                              : 3
 16-bit 4-to-1 multiplexer                             : 1
 3-bit 4-to-1 multiplexer                              : 2
 8-bit 4-to-1 multiplexer                              : 3
 8-bit 8-to-1 multiplexer                              : 3
# Tristates                                            : 14
 5-bit tristate buffer                                 : 2
 8-bit tristate buffer                                 : 12
# Xors                                                 : 3
 1-bit xor2                                            : 1
 1-bit xor8                                            : 1
 8-bit xor2                                            : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_3> for best encoding.
Optimizing FSM <adm3a/state> on signal <state[1:20]> with one-hot encoding.
-------------------------------
 State | Encoding
-------------------------------
 00000 | 00000000000000100000
 00001 | 00000000000000000010
 00010 | 00000000000001000000
 00011 | 00000000000010000000
 00100 | 00000000000000000001
 00101 | 00000000000100000000
 00110 | 00000000001000000000
 00111 | 00000000010000000000
 01000 | 00000000000000001000
 01001 | 00000000000000000100
 01010 | 00000000100000000000
 01011 | 00000010000000000000
 01100 | 00000100000000000000
 01101 | 00001000000000000000
 01110 | 00000001000000000000
 01111 | 00010000000000000000
 10000 | 00000000000000010000
 10001 | 00100000000000000000
 10010 | 10000000000000000000
 10011 | 01000000000000000000
-------------------------------
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <adm3a/display/fchsta> on signal <fchsta[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 11
 11    | 10
-------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <cpu/state> on signal <state[1:41]> with speed1 encoding.
-----------------------------------------------------
 State  | Encoding
-----------------------------------------------------
 000001 | 10000000000000000000000000000000000000000
 000010 | 01000000000000000000000000000000000000000
 000011 | 00100000000000000000000000000000000000000
 000100 | 00010000000000000000000000000000000000000
 000101 | 00000000100000000000000000000000000000000
 000110 | 00000000010000000000000000000000000000001
 000111 | 00000010000000000000000000000000000000001
 001000 | 00000000000000001000000000000000000000001
 001001 | 00000000000000000010000000000000000000001
 001010 | 00000000000000000000100000000000000000001
 001011 | 00000000000000000000010000000000000000001
 001100 | 00000000001000000001000000000000000000000
 001101 | 00000000000000000000000000100000000000001
 001110 | 00000001000000000000000000000000000000000
 001111 | 00000000000010000000000000000000000000000
 010000 | 00000000000001000000000000000000000000000
 010001 | 00000000001000100000000000000000000000000
 010010 | 00000100000000000000000000000000000000000
 010011 | 00000000000000000000000000000000100000000
 010100 | 00000000001100000000000000000000000000000
 010101 | 00000000000000000000001000000000000000001
 010110 | 00000000000000000000000000000010000000000
 010111 | 00000000000000000000000000000000000100000
 011000 | 00000000000000000000000000000000000010001
 011001 | 00000000000000000000000000000001000000000
 011010 | 00000000000000000000000000000000000001000
 011011 | 00000000000000000000000000000000000000100
 011100 | 00000000000000000000000000000000000000011
 011101 | 00000000001000010000000000000000000000000
 011110 | 00000000001000000000000100000000000000000
 011111 | 00000000001000000000000001000000000000000
 0XXXXX | unreached
 100000 | 00000000001000000100000000000000000000000
 100001 | 00000000000000000000000010000000000000000
 100010 | 00001000000000000000000000000000000000001
 100011 | 00000000000000000000000000001000000000001
 100100 | 00000000000000000000000000000000010000001
 100101 | 00000000001000000000000000010000000000000
 100110 | 00000000001000000000000000000000001000000
 100111 | 00000000001000000000000000000100000000000
-----------------------------------------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <intc/state> on signal <state[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 0000  | 00
 0001  | 01
 0010  | 11
-------------------
Loading device for application Rf_Device from file '3s1000.nph' in environment C:\Xilinx.
WARNING:Xst:2404 -  FFs/Latches <curchr<7:7>> (without init value) have a constant value of 0 in block <chrmemmap>.
WARNING:Xst:2404 -  FFs/Latches <chrdatw<7:7>> (without init value) have a constant value of 0 in block <terminal>.
WARNING:Xst:2404 -  FFs/Latches <rowchr<7:7>> (without init value) have a constant value of 0 in block <terminal>.
INFO:Xst:1651 - Address input of ROM <rom/Mrom_datao> is tied to register <cpu/addr>.
INFO:Xst:1650 - The register is removed and the ROM is implemented as read-only block RAM.
WARNING:Xst:1710 - FF/Latch  <datai_0> (without init value) has a constant value of 0 in block <select>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <datai_1> (without init value) has a constant value of 0 in block <select>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <datai_2> (without init value) has a constant value of 0 in block <select>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <datai_3> (without init value) has a constant value of 0 in block <select>.
INFO:Xst:2261 - The FF/Latch <rgb_r_0> in Unit <vga> is equivalent to the following 8 FFs/Latches, which will be removed : <rgb_r_1> <rgb_r_2> <rgb_r_3> <rgb_r_4> <rgb_r_5> <rgb_r_6> <rgb_r_7> <rgb_r_8> 
WARNING:Xst:1291 - FF/Latch <cmattri_5> is unconnected in block <terminal>.
WARNING:Xst:1291 - FF/Latch <cmattri_6> is unconnected in block <terminal>.
WARNING:Xst:1291 - FF/Latch <cmattri_7> is unconnected in block <terminal>.
WARNING:Xst:1291 - FF/Latch <blank_r_3> is unconnected in block <vgai>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 4
# RAMs                                                 : 5
 1024x8-bit single-port block RAM                      : 1
 1920x5-bit dual-port block RAM                        : 1
 1920x8-bit dual-port distributed RAM                  : 1
 1920x8-bit single-port block RAM                      : 1
 2048x8-bit single-port block RAM                      : 1
# ROMs                                                 : 3
 2048x8-bit ROM                                        : 1
 4x1-bit ROM                                           : 1
 4x16-bit ROM                                          : 1
# Multipliers                                          : 2
 9x6-bit multiplier                                    : 1
 9x8-bit multiplier                                    : 1
# Adders/Subtractors                                   : 55
 10-bit subtractor                                     : 1
 11-bit adder                                          : 5
 11-bit adder carry out                                : 1
 11-bit addsub                                         : 1
 13-bit adder                                          : 1
 16-bit adder                                          : 7
 16-bit addsub                                         : 1
 16-bit subtractor                                     : 1
 17-bit adder                                          : 8
 32-bit adder                                          : 6
 32-bit subtractor                                     : 3
 4-bit adder carry out                                 : 1
 5-bit adder                                           : 1
 5-bit subtractor                                      : 1
 6-bit adder                                           : 1
 6-bit subtractor                                      : 2
 8-bit adder                                           : 1
 8-bit adder carry out                                 : 3
 8-bit addsub                                          : 3
 9-bit adder                                           : 3
 9-bit subtractor                                      : 4
# Counters                                             : 6
 32-bit up counter                                     : 1
 4-bit up counter                                      : 1
 5-bit up counter                                      : 2
 7-bit up counter                                      : 1
 8-bit up counter                                      : 1
# Accumulators                                         : 1
 11-bit up accumulator                                 : 1
# Registers                                            : 580
 Flip-Flops                                            : 580
# Latches                                              : 12
 6-bit latch                                           : 4
 8-bit latch                                           : 8
# Comparators                                          : 33
 11-bit comparator equal                               : 1
 11-bit comparator greatequal                          : 1
 11-bit comparator greater                             : 1
 11-bit comparator less                                : 5
 12-bit comparator greater                             : 2
 32-bit comparator greatequal                          : 1
 4-bit comparator equal                                : 1
 4-bit comparator greater                              : 2
 5-bit comparator greatequal                           : 1
 5-bit comparator less                                 : 1
 6-bit comparator equal                                : 4
 7-bit comparator greatequal                           : 1
 7-bit comparator less                                 : 1
 8-bit comparator greatequal                           : 4
 8-bit comparator greater                              : 1
 8-bit comparator less                                 : 2
 8-bit comparator lessequal                            : 4
# Multiplexers                                         : 29
 1-bit 4-to-1 multiplexer                              : 17
 1-bit 8-to-1 multiplexer                              : 3
 16-bit 4-to-1 multiplexer                             : 1
 3-bit 4-to-1 multiplexer                              : 2
 8-bit 4-to-1 multiplexer                              : 3
 8-bit 8-to-1 multiplexer                              : 3
# Xors                                                 : 3
 1-bit xor2                                            : 1
 1-bit xor8                                            : 1
 8-bit xor2                                            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1988 - Unit <chrmemmap>: instances <Mcompar__cmp_ge0001>, <Mcompar__cmp_lt0000> of unit <LPM_COMPARE_5> and unit <LPM_COMPARE_7> are dual, second instance is removed
WARNING:Xst:1988 - Unit <chrmemmap>: instances <Mcompar__cmp_ge0002>, <Mcompar__cmp_lt0001> of unit <LPM_COMPARE_6> and unit <LPM_COMPARE_8> are dual, second instance is removed
WARNING:Xst:1989 - Unit <terminal>: instances <Mcompar__cmp_gt0000>, <Mcompar__cmp_gt0003> of unit <LPM_COMPARE_13> are equivalent, second instance is removed
WARNING:Xst:1291 - FF/Latch <lincnt_0> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <lincnt_1> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <lincnt_2> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <lincnt_3> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <lincnt_4> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8421> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8401> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8411> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8431> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8441> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8451> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8461> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8471> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8481> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8491> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8501> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8511> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8521> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8531> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8541> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8551> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8561> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8571> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8581> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8591> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8601> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8611> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8621> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8631> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8641> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8651> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8661> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8671> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8681> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8691> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8701> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8711> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8721> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8731> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8741> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8751> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8761> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8771> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8781> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8791> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8801> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8811> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8821> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8831> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8841> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8851> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8861> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8871> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8881> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8891> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8901> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8911> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8921> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8931> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8941> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8951> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8961> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8971> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8981> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem8991> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9001> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9011> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9021> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9051> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9031> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9041> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9061> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9071> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9081> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9091> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9101> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9111> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9121> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9131> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9141> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9151> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9161> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9171> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9181> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9191> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9201> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9211> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9221> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9231> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9241> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9251> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9261> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9271> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9281> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9291> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9301> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9311> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9321> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9331> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9361> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9341> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9351> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9371> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9381> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9391> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9401> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9411> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9421> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9431> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9441> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9451> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9461> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9471> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9481> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9491> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9501> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9511> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9521> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9531> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9541> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9551> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9561> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9571> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9581> is unconnected in block <chrmemmap>.
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem9591> is unconnected in block <chrmemmap>.
WARNING:Xst:1710 - FF/Latch  <scnadr_0> (without init value) has a constant value of 0 in block <chrmemmap>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <scnadr_1> (without init value) has a constant value of 0 in block <chrmemmap>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <scnadr_2> (without init value) has a constant value of 0 in block <chrmemmap>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <scnadr_3> (without init value) has a constant value of 0 in block <chrmemmap>.
WARNING:Xst:2040 - Unit testbench: 21 multi-source signals are replaced by logic (pull-up yes): adm3a/cmattr<0>, adm3a/cmattr<1>, adm3a/cmattr<2>, adm3a/cmattr<3>, adm3a/cmattr<4>, adm3a/cmdata<0>, adm3a/cmdata<1>, adm3a/cmdata<2>, adm3a/cmdata<3>, adm3a/cmdata<4>, adm3a/cmdata<5>, adm3a/cmdata<6>, adm3a/cmdata<7>, N180, N182, N184, N186, N188, N190, N192, N194.
WARNING:Xst:2042 - Unit chrmemmap: 13 internal tristates are replaced by logic (pull-up yes): attr<0>, attr<1>, attr<2>, attr<3>, attr<4>, data<0>, data<1>, data<2>, data<3>, data<4>, data<5>, data<6>, data<7>.

Optimizing unit <testbench> ...

Optimizing unit <alu> ...

Optimizing unit <ps2_kbd> ...

Optimizing unit <sync_2> ...

Optimizing unit <sync_1> ...

Optimizing unit <vga> ...

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <adm3a/display/vgai/blank_r_3> is unconnected in block <testbench>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block testbench, actual ratio is 33.
FlipFlop adm3a/cmaddr_0 has been replicated 5 time(s)
FlipFlop adm3a/cmaddr_1 has been replicated 5 time(s)
FlipFlop adm3a/cmaddr_2 has been replicated 5 time(s)
FlipFlop adm3a/cmaddr_3 has been replicated 5 time(s)
FlipFlop adm3a/display/chrcnt_0 has been replicated 1 time(s)
FlipFlop adm3a/display/chrcnt_1 has been replicated 1 time(s)
FlipFlop adm3a/display/chrcnt_2 has been replicated 1 time(s)
FlipFlop adm3a/display/chrcnt_3 has been replicated 1 time(s)
FlipFlop adm3a/display/rowcnt_0 has been replicated 1 time(s)
FlipFlop adm3a/vgai/sc_r_5 has been replicated 1 time(s)
FlipFlop cpu/addr_0 has been replicated 1 time(s)
FlipFlop cpu/addr_1 has been replicated 2 time(s)
FlipFlop cpu/addr_2 has been replicated 2 time(s)
FlipFlop cpu/addr_3 has been replicated 1 time(s)
FlipFlop cpu/readio has been replicated 1 time(s)

Final Macro Processing ...

Processing Unit <testbench> :
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <adm3a/state_FFd7> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <cpu/state_FFd3> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:2387 - HDL ADVISOR - A 3-bit shift register was found for signal <adm3a/vgai/sc_r_7> and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <adm3a/vgai/ps2_clk_r_2> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <adm3a/display/vgai/blank_r_2> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:2387 - HDL ADVISOR - A 3-bit shift register was found for signal <adm3a/display/vgai/hsync_r_3> and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
Unit <testbench> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 668
 Flip-Flops                                            : 668

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : testbench.ngr
Top Level Output File Name         : testbench
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 54

Cell Usage :
# BELS                             : 6513
#      GND                         : 1
#      INV                         : 101
#      LUT1                        : 231
#      LUT2                        : 439
#      LUT2_D                      : 36
#      LUT2_L                      : 5
#      LUT3                        : 1122
#      LUT3_D                      : 37
#      LUT3_L                      : 25
#      LUT4                        : 2308
#      LUT4_D                      : 82
#      LUT4_L                      : 236
#      MULT_AND                    : 28
#      MUXCY                       : 655
#      MUXF5                       : 612
#      MUXF6                       : 175
#      MUXF7                       : 59
#      MUXF8                       : 23
#      VCC                         : 1
#      XORCY                       : 337
# FlipFlops/Latches                : 756
#      FD                          : 7
#      FDC                         : 23
#      FDCE                        : 56
#      FDE                         : 324
#      FDE_1                       : 8
#      FDP                         : 6
#      FDPE                        : 21
#      FDR                         : 81
#      FDRE                        : 40
#      FDRE_1                      : 42
#      FDRS                        : 46
#      FDRSE                       : 10
#      FDS                         : 3
#      FDSE                        : 1
#      LDCE                        : 56
#      LDE_1                       : 32
# RAMS                             : 844
#      RAM16X1D                    : 840
#      RAMB16_S9                   : 3
#      RAMB16_S9_S9                : 1
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 52
#      IBUF                        : 2
#      IOBUF                       : 8
#      OBUF                        : 42
# MULTs                            : 2
#      MULT18X18                   : 2
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s1000ft256-4 

 Number of Slices:                    2416  out of   7680    31%  
 Number of Slice Flip Flops:           756  out of  15360     4%  
 Number of 4 input LUTs:              6302  out of  15360    41%  
    Number used as logic:             4622
    Number used as RAMs:              1680
 Number of IOs:                         54
 Number of bonded IOBs:                 54  out of    173    31%  
 Number of BRAMs:                        4  out of     24    16%  
 Number of MULT18X18s:                   2  out of     24     8%  
 Number of GCLKs:                        2  out of      8    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------------------------+--------------------------------+-------+
Clock Signal                                         | Clock buffer(FF name)          | Load  |
-----------------------------------------------------+--------------------------------+-------+
clock                                                | BUFGP                          | 1509  |
reset_n                                              | BUFGP                          | 32    |
select1/selectd/_and0000(select1/selectd/_and00001:O)| NONE(*)(select1/selectd/mask_5)| 14    |
select1/selectc/_and0000(select1/selectc/_and00001:O)| NONE(*)(select1/selectc/comp_2)| 14    |
select1/selectb/_and0000(select1/selectb/_and00001:O)| NONE(*)(select1/selectb/mask_7)| 14    |
select1/selecta/_and0000(select1/selecta/_and00001:O)| NONE(*)(select1/selecta/mask_7)| 14    |
-----------------------------------------------------+--------------------------------+-------+
(*) These 4 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------------------------------------+-------+
Control Signal                     | Buffer(FF name)                                      | Load  |
-----------------------------------+------------------------------------------------------+-------+
reset(reset1_INV_0:O)              | NONE(adm3a/display/vgai/gen_syncs_fit.vsync/cnt_r_10)| 162   |
-----------------------------------+------------------------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 21.437ns (Maximum Frequency: 46.649MHz)
   Minimum input arrival time before clock: 8.841ns
   Maximum output required time after clock: 18.905ns
   Maximum combinational path delay: 7.342ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clock'
  Clock period: 21.437ns (frequency: 46.649MHz)
  Total number of paths / destination ports: 238171 / 9398
-------------------------------------------------------------------------
Delay:               21.437ns (Levels of Logic = 15)
  Source:            adm3a/display/curchr_6 (FF)
  Destination:       adm3a/display/pixeldata_10 (FF)
  Source Clock:      clock rising
  Destination Clock: clock rising

  Data Path: adm3a/display/curchr_6 to adm3a/display/pixeldata_10
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.720   0.877  adm3a/display/curchr_6 (adm3a/display/curchr_6)
     MULT18X18:A0->P0     39   1.779   2.088  adm3a/display/Mmult__mult0002 (adm3a/display/_mult0002<0>)
     LUT2:I1->O            1   0.551   0.000  adm3a/display/Madd__addsub0001_lut<0>_1 (adm3a/display/Madd__addsub0001_lut<0>)
     MUXCY:S->O            1   0.500   0.000  adm3a/display/Madd__addsub0001_cy<0> (adm3a/display/Madd__addsub0001_cy<0>)
     MUXCY:CI->O           1   0.064   0.000  adm3a/display/Madd__addsub0001_cy<1> (adm3a/display/Madd__addsub0001_cy<1>)
     XORCY:CI->O         145   0.904   2.526  adm3a/display/Madd__addsub0001_xor<2> (adm3a/display/_addsub0001<2>)
     LUT4_D:I3->O          1   0.551   0.869  adm3a/display/crom/Mrom_data145_SW3 (N16984)
     LUT4:I2->O            7   0.551   1.092  adm3a/display/crom/Mrom_data145 (adm3a/display/N149)
     LUT4:I3->O            1   0.551   0.827  adm3a/display/chradr<4>173 (adm3a/display/N19411)
     LUT4:I3->O            1   0.551   0.000  adm3a/display/chradr<7>1555_G (N17173)
     MUXF5:I1->O           1   0.360   0.827  adm3a/display/chradr<7>1555 (adm3a/display/chradr<7>15_map5531)
     LUT4:I3->O            1   0.551   0.827  adm3a/display/chradr<7>1557 (adm3a/display/chradr<7>12)
     LUT4:I3->O            1   0.551   0.000  adm3a/display/chradr<9>_f5_2_F (N17190)
     MUXF5:I0->O           1   0.360   0.827  adm3a/display/chradr<9>_f5_2 (adm3a/display/chradr<9>_f53)
     LUT4_D:I3->O          1   0.551   0.827  adm3a/display/chradr<10>111411 (adm3a/display/N2731)
     LUT4:I3->O            1   0.551   0.000  adm3a/display/_mux0011<10>1 (adm3a/display/_mux0011<10>)
     FDE:D                     0.203          adm3a/display/pixeldata_10
    ----------------------------------------
    Total                     21.437ns (9.849ns logic, 11.588ns route)
                                       (45.9% logic, 54.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clock'
  Total number of paths / destination ports: 639 / 639
-------------------------------------------------------------------------
Offset:              8.841ns (Levels of Logic = 2)
  Source:            reset_n (PAD)
  Destination:       cpu/readmem (FF)
  Destination Clock: clock rising

  Data Path: reset_n to cpu/readmem
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     BUFGP:I->O          248   0.401   3.090  reset_n_BUFGP (reset_n_BUFGP)
     INV:I->O            367   0.551   3.772  reset1_INV_0 (reset)
     FDRSE:R                   1.026          cpu/writeio
    ----------------------------------------
    Total                      8.841ns (1.978ns logic, 6.863ns route)
                                       (22.4% logic, 77.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectd/_and0000'
  Total number of paths / destination ports: 14 / 14
-------------------------------------------------------------------------
Offset:              2.474ns (Levels of Logic = 1)
  Source:            data<6> (PAD)
  Destination:       select1/selectd/mask_6 (LATCH)
  Destination Clock: select1/selectd/_and0000 falling

  Data Path: data<6> to select1/selectd/mask_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N16300)
     LDCE:D                    0.203          select1/selectd/mask_6
    ----------------------------------------
    Total                      2.474ns (1.024ns logic, 1.450ns route)
                                       (41.4% logic, 58.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectc/_and0000'
  Total number of paths / destination ports: 14 / 14
-------------------------------------------------------------------------
Offset:              2.474ns (Levels of Logic = 1)
  Source:            data<6> (PAD)
  Destination:       select1/selectc/mask_6 (LATCH)
  Destination Clock: select1/selectc/_and0000 falling

  Data Path: data<6> to select1/selectc/mask_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N16300)
     LDCE:D                    0.203          select1/selectc/mask_6
    ----------------------------------------
    Total                      2.474ns (1.024ns logic, 1.450ns route)
                                       (41.4% logic, 58.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectb/_and0000'
  Total number of paths / destination ports: 14 / 14
-------------------------------------------------------------------------
Offset:              2.474ns (Levels of Logic = 1)
  Source:            data<6> (PAD)
  Destination:       select1/selectb/mask_6 (LATCH)
  Destination Clock: select1/selectb/_and0000 falling

  Data Path: data<6> to select1/selectb/mask_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N16300)
     LDCE:D                    0.203          select1/selectb/mask_6
    ----------------------------------------
    Total                      2.474ns (1.024ns logic, 1.450ns route)
                                       (41.4% logic, 58.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selecta/_and0000'
  Total number of paths / destination ports: 14 / 14
-------------------------------------------------------------------------
Offset:              2.474ns (Levels of Logic = 1)
  Source:            data<6> (PAD)
  Destination:       select1/selecta/mask_6 (LATCH)
  Destination Clock: select1/selecta/_and0000 falling

  Data Path: data<6> to select1/selecta/mask_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O          19   0.821   1.450  data_6_IOBUF (N16300)
     LDCE:D                    0.203          select1/selecta/mask_6
    ----------------------------------------
    Total                      2.474ns (1.024ns logic, 1.450ns route)
                                       (41.4% logic, 58.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'
  Total number of paths / destination ports: 2377 / 47
-------------------------------------------------------------------------
Offset:              18.905ns (Levels of Logic = 8)
  Source:            cpu/addr_4 (FF)
  Destination:       data<7> (PAD)
  Source Clock:      clock rising

  Data Path: cpu/addr_4 to data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              8   0.720   1.278  cpu/addr_4 (cpu/addr_4)
     LUT4:I1->O            3   0.551   1.246  select1/selacc426 (select1/selacc4_map5652)
     LUT2:I0->O            3   0.551   1.246  select1/selacc454 (select1/selacc)
     LUT4:I0->O            9   0.551   1.150  select1/selecta/_and0001_inv1 (select1/selecta/_and0001_inv)
     LUT4:I3->O            1   0.551   0.996  N186LogicTrst63_SW0 (N17403)
     LUT4:I1->O            1   0.551   1.140  N186LogicTrst63 (N186LogicTrst_map6210)
     LUT4:I0->O            1   0.551   0.827  N186LogicTrst126_SW0 (N17405)
     LUT4:I3->O            1   0.551   0.801  N186LogicTrst126 (data_4_IOBUF)
     IOBUF:I->IO               5.644          data_4_IOBUF (data<4>)
    ----------------------------------------
    Total                     18.905ns (10.221ns logic, 8.684ns route)
                                       (54.1% logic, 45.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selecta/_and0000'
  Total number of paths / destination ports: 840 / 8
-------------------------------------------------------------------------
Offset:              18.295ns (Levels of Logic = 8)
  Source:            select1/selecta/mask_1 (LATCH)
  Destination:       data<7> (PAD)
  Source Clock:      select1/selecta/_and0000 falling

  Data Path: select1/selecta/mask_1 to data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             7   0.633   1.405  select1/selecta/mask_1 (select1/selecta/mask_1)
     LUT4:I0->O            1   0.551   0.000  _and0000_inv181 (N18091)
     MUXF5:I1->O           1   0.360   1.140  _and0000_inv18_f5 (_and0000_inv_map5862)
     LUT4:I0->O            1   0.551   1.140  _and0000_inv108 (_and0000_inv_map5889)
     LUT4:I0->O            9   0.551   1.150  _and0000_inv211 (_and0000_inv)
     LUT4:I3->O            1   0.551   1.140  N180LogicTrst120 (N180LogicTrst1_map5994)
     LUT4:I0->O           16   0.551   1.576  N180LogicTrst142 (N269)
     LUT3:I0->O            1   0.551   0.801  N194LogicTrst108 (data_0_IOBUF)
     IOBUF:I->IO               5.644          data_0_IOBUF (data<0>)
    ----------------------------------------
    Total                     18.295ns (9.943ns logic, 8.352ns route)
                                       (54.3% logic, 45.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectd/_and0000'
  Total number of paths / destination ports: 624 / 8
-------------------------------------------------------------------------
Offset:              17.289ns (Levels of Logic = 8)
  Source:            select1/selectd/mask_1 (LATCH)
  Destination:       data<7> (PAD)
  Source Clock:      select1/selectd/_and0000 falling

  Data Path: select1/selectd/mask_1 to data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             7   0.633   1.405  select1/selectd/mask_1 (select1/selectd/mask_1)
     LUT4:I0->O            1   0.551   0.000  select1/selectd/selectout791 (N18071)
     MUXF5:I1->O           1   0.360   1.140  select1/selectd/selectout79_f5 (select1/selectd/selectout_map5690)
     LUT4_D:I0->O          3   0.551   0.975  select1/selectd/selectout169 (select1/selectd/selectout_map5717)
     LUT3:I2->O           17   0.551   1.371  adm3a/_and00001 (adm3a/_and0000)
     LUT4:I3->O            1   0.551   0.827  N182LogicTrst113 (N182LogicTrst_map6158)
     LUT4:I3->O            1   0.551   0.827  N182LogicTrst126_SW0 (N17397)
     LUT4:I3->O            1   0.551   0.801  N182LogicTrst126 (data_6_IOBUF)
     IOBUF:I->IO               5.644          data_6_IOBUF (data<6>)
    ----------------------------------------
    Total                     17.289ns (9.943ns logic, 7.346ns route)
                                       (57.5% logic, 42.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectb/_and0000'
  Total number of paths / destination ports: 840 / 8
-------------------------------------------------------------------------
Offset:              16.855ns (Levels of Logic = 8)
  Source:            select1/selectb/comp_1 (LATCH)
  Destination:       data<7> (PAD)
  Source Clock:      select1/selectb/_and0000 falling

  Data Path: select1/selectb/comp_1 to data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.633   1.246  select1/selectb/comp_1 (select1/selectb/comp_1)
     LUT4:I0->O            1   0.551   0.000  select1/select248_SW02 (N18126)
     MUXF5:I0->O           2   0.360   1.072  select1/select248_SW0_f5 (N17258)
     LUT4:I1->O            1   0.551   0.000  select1/select2482 (N18128)
     MUXF5:I0->O           2   0.360   1.216  select1/select248_f5 (select1/select2_map5800)
     LUT4:I0->O            9   0.551   1.192  ram/_and0000_inv1 (ram/_and0000_inv)
     LUT4:I2->O           16   0.551   1.576  N180LogicTrst142 (N269)
     LUT3:I0->O            1   0.551   0.801  N194LogicTrst108 (data_0_IOBUF)
     IOBUF:I->IO               5.644          data_0_IOBUF (data<0>)
    ----------------------------------------
    Total                     16.855ns (9.752ns logic, 7.103ns route)
                                       (57.9% logic, 42.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectc/_and0000'
  Total number of paths / destination ports: 552 / 8
-------------------------------------------------------------------------
Offset:              18.172ns (Levels of Logic = 8)
  Source:            select1/selectc/mask_1 (LATCH)
  Destination:       data<7> (PAD)
  Source Clock:      select1/selectc/_and0000 falling

  Data Path: select1/selectc/mask_1 to data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             7   0.633   1.405  select1/selectc/mask_1 (select1/selectc/mask_1)
     LUT4:I0->O            1   0.551   0.000  select1/selectc/selectout1511 (N18101)
     MUXF5:I1->O           2   0.360   1.216  select1/selectc/selectout151_f5 (select1/selectc/selectout_map6331)
     LUT4_D:I0->O          1   0.551   0.827  select1/selectc/selectout169_1 (select1/selectc/selectout169)
     LUT4_D:I3->O         12   0.551   1.457  intc/_not0027_SW0 (intc/_and0009)
     LUT2:I0->O            5   0.551   0.947  intc/_or0000_inv1 (intc/_or0000_inv)
     LUT4:I3->O           16   0.551   1.576  N180LogicTrst142 (N269)
     LUT3:I0->O            1   0.551   0.801  N194LogicTrst108 (data_0_IOBUF)
     IOBUF:I->IO               5.644          data_0_IOBUF (data<0>)
    ----------------------------------------
    Total                     18.172ns (9.943ns logic, 8.229ns route)
                                       (54.7% logic, 45.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'reset_n'
  Total number of paths / destination ports: 32 / 8
-------------------------------------------------------------------------
Offset:              15.954ns (Levels of Logic = 7)
  Source:            select1/selectb/datai_3 (LATCH)
  Destination:       data<3> (PAD)
  Source Clock:      reset_n falling

  Data Path: select1/selectb/datai_3 to data<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE_1:G->Q            1   0.633   0.869  select1/selectb/datai_3 (select1/selectb/datai_3)
     LUT4:I2->O            1   0.551   0.996  N188LogicTrst26 (N188LogicTrst_map6009)
     LUT4:I1->O            1   0.551   0.827  N188LogicTrst34 (N188LogicTrst_map6011)
     LUT4:I3->O            1   0.551   0.869  N188LogicTrst61 (N188LogicTrst_map6017)
     LUT3:I2->O            1   0.551   1.140  N188LogicTrst95_SW0 (N17625)
     LUT4:I0->O            1   0.551   0.869  N188LogicTrst95 (N188LogicTrst_map6023)
     LUT3:I2->O            1   0.551   0.801  N188LogicTrst108 (data_3_IOBUF)
     IOBUF:I->IO               5.644          data_3_IOBUF (data<3>)
    ----------------------------------------
    Total                     15.954ns (9.583ns logic, 6.371ns route)
                                       (60.1% logic, 39.9% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Delay:               7.342ns (Levels of Logic = 2)
  Source:            ps2_data (PAD)
  Destination:       diag<4> (PAD)

  Data Path: ps2_data to diag<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.821   0.877  ps2_data_IBUF (ps2_data_IBUF)
     OBUF:I->O                 5.644          diag_4_OBUF (diag<4>)
    ----------------------------------------
    Total                      7.342ns (6.465ns logic, 0.877ns route)
                                       (88.1% logic, 11.9% route)

=========================================================================
CPU : 243.39 / 243.99 s | Elapsed : 243.00 / 244.00 s
 
--> 

Total memory usage is 241168 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  162 (   0 filtered)
Number of infos    :   14 (   0 filtered)

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