Subversion Repositories cpu8080

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Release 8.2.02i Trace 
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

C:\Xilinx\bin\nt\trce.exe -ise C:/Xilinx/ISEexamples/cpu8080/cpu8080.ise
-intstyle ise -e 3 -l 3 -s 4 -xml testbench testbench.ncd -o testbench.twr
testbench.pcf -ucf cpu8080.ucf

Design file:              testbench.ncd
Physical constraint file: testbench.pcf
Device,speed:             xc3s1000,-4 (PRODUCTION 1.39 2006-07-07)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clock
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
data<0>     |    3.965(R)|    0.042(R)|clock_BUFGP       |   0.000|
            |    1.716(F)|    1.081(F)|clock_BUFGP       |   0.000|
data<1>     |    3.965(R)|   -0.732(R)|clock_BUFGP       |   0.000|
            |    2.447(F)|    0.996(F)|clock_BUFGP       |   0.000|
data<2>     |    3.806(R)|   -0.355(R)|clock_BUFGP       |   0.000|
            |    1.738(F)|    1.048(F)|clock_BUFGP       |   0.000|
data<3>     |    5.193(R)|   -0.463(R)|clock_BUFGP       |   0.000|
            |    1.689(F)|    1.447(F)|clock_BUFGP       |   0.000|
data<4>     |    3.936(R)|   -0.405(R)|clock_BUFGP       |   0.000|
            |    1.403(F)|    1.117(F)|clock_BUFGP       |   0.000|
data<5>     |    3.854(R)|    0.020(R)|clock_BUFGP       |   0.000|
            |    1.698(F)|    1.436(F)|clock_BUFGP       |   0.000|
data<6>     |    3.854(R)|   -0.937(R)|clock_BUFGP       |   0.000|
            |    1.673(F)|    1.399(F)|clock_BUFGP       |   0.000|
data<7>     |    4.793(R)|    0.845(R)|clock_BUFGP       |   0.000|
            |    2.873(F)|    0.161(F)|clock_BUFGP       |   0.000|
ps2_clk     |    3.956(R)|   -1.538(R)|clock_BUFGP       |   0.000|
ps2_data    |    3.986(R)|   -1.572(R)|clock_BUFGP       |   0.000|
------------+------------+------------+------------------+--------+

Clock clock to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
addr<0>     |   11.994(R)|clock_BUFGP       |   0.000|
addr<1>     |   10.876(R)|clock_BUFGP       |   0.000|
addr<2>     |   10.900(R)|clock_BUFGP       |   0.000|
addr<3>     |   11.231(R)|clock_BUFGP       |   0.000|
addr<4>     |   11.054(R)|clock_BUFGP       |   0.000|
addr<5>     |   10.716(R)|clock_BUFGP       |   0.000|
addr<6>     |   10.985(R)|clock_BUFGP       |   0.000|
addr<7>     |   11.936(R)|clock_BUFGP       |   0.000|
addr<8>     |   12.143(R)|clock_BUFGP       |   0.000|
addr<9>     |   11.668(R)|clock_BUFGP       |   0.000|
addr<10>    |   10.082(R)|clock_BUFGP       |   0.000|
addr<11>    |   10.764(R)|clock_BUFGP       |   0.000|
addr<12>    |   11.272(R)|clock_BUFGP       |   0.000|
addr<13>    |   11.196(R)|clock_BUFGP       |   0.000|
addr<14>    |   12.084(R)|clock_BUFGP       |   0.000|
addr<15>    |   14.492(R)|clock_BUFGP       |   0.000|
b<0>        |   11.515(R)|clock_BUFGP       |   0.000|
b<1>        |   12.241(R)|clock_BUFGP       |   0.000|
b<2>        |   13.320(R)|clock_BUFGP       |   0.000|
data<0>     |   23.632(R)|clock_BUFGP       |   0.000|
            |   13.589(F)|clock_BUFGP       |   0.000|
data<1>     |   24.480(R)|clock_BUFGP       |   0.000|
            |   13.845(F)|clock_BUFGP       |   0.000|
data<2>     |   24.410(R)|clock_BUFGP       |   0.000|
            |   13.003(F)|clock_BUFGP       |   0.000|
data<3>     |   24.240(R)|clock_BUFGP       |   0.000|
            |   15.840(F)|clock_BUFGP       |   0.000|
data<4>     |   23.917(R)|clock_BUFGP       |   0.000|
            |   13.826(F)|clock_BUFGP       |   0.000|
data<5>     |   23.894(R)|clock_BUFGP       |   0.000|
            |   13.205(F)|clock_BUFGP       |   0.000|
data<6>     |   25.143(R)|clock_BUFGP       |   0.000|
            |   14.217(F)|clock_BUFGP       |   0.000|
data<7>     |   24.504(R)|clock_BUFGP       |   0.000|
            |   13.067(F)|clock_BUFGP       |   0.000|
diag<0>     |   13.672(R)|clock_BUFGP       |   0.000|
diag<1>     |   14.125(R)|clock_BUFGP       |   0.000|
diag<2>     |   10.832(R)|clock_BUFGP       |   0.000|
diag<5>     |   11.004(R)|clock_BUFGP       |   0.000|
diag<6>     |   11.122(R)|clock_BUFGP       |   0.000|
diag<7>     |   10.831(R)|clock_BUFGP       |   0.000|
g<0>        |   11.901(R)|clock_BUFGP       |   0.000|
g<1>        |   12.611(R)|clock_BUFGP       |   0.000|
g<2>        |   16.391(R)|clock_BUFGP       |   0.000|
hsync_n     |    7.261(R)|clock_BUFGP       |   0.000|
inta        |   16.641(R)|clock_BUFGP       |   0.000|
intr        |   14.027(F)|clock_BUFGP       |   0.000|
r<0>        |   11.869(R)|clock_BUFGP       |   0.000|
r<1>        |   12.611(R)|clock_BUFGP       |   0.000|
r<2>        |   16.497(R)|clock_BUFGP       |   0.000|
readio      |   11.892(R)|clock_BUFGP       |   0.000|
readmem     |   11.470(R)|clock_BUFGP       |   0.000|
vsync_n     |   11.388(R)|clock_BUFGP       |   0.000|
writeio     |   10.297(R)|clock_BUFGP       |   0.000|
writemem    |    9.754(R)|clock_BUFGP       |   0.000|
------------+------------+------------------+--------+

Clock reset_n to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
data<0>     |   16.112(F)|reset_n_BUFGP     |   0.000|
data<1>     |   17.018(F)|reset_n_BUFGP     |   0.000|
data<2>     |   15.481(F)|reset_n_BUFGP     |   0.000|
data<3>     |   17.519(F)|reset_n_BUFGP     |   0.000|
data<4>     |   15.991(F)|reset_n_BUFGP     |   0.000|
data<5>     |   15.232(F)|reset_n_BUFGP     |   0.000|
data<6>     |   17.843(F)|reset_n_BUFGP     |   0.000|
data<7>     |   16.272(F)|reset_n_BUFGP     |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clock
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clock          |   20.967|    8.556|   10.449|    8.106|
reset_n        |   12.576|   12.576|    7.310|    7.310|
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock reset_n
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clock          |         |         |   10.315|         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
ps2_clk        |diag<3>        |   13.322|
ps2_data       |diag<4>        |   12.870|
---------------+---------------+---------+


Analysis completed Sat Nov 11 00:55:33 2006
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 182 MB