Subversion Repositories cpu8080

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Release 8.2.02i Trace 
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

C:\Xilinx\bin\nt\trce.exe -ise C:/Xilinx/ISEexamples/cpu8080/cpu8080.ise
-intstyle ise -e 3 -l 3 -s 4 -xml testbench testbench.ncd -o testbench.twr
testbench.pcf -ucf cpu8080.ucf

Design file:              testbench.ncd
Physical constraint file: testbench.pcf
Device,speed:             xc3s1000,-4 (PRODUCTION 1.39 2006-07-07)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clock
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
data<0>     |    4.255(R)|   -1.186(R)|clock_BUFGP       |   0.000|
            |    3.683(F)|   -0.440(F)|clock_BUFGP       |   0.000|
data<1>     |    4.053(R)|   -0.239(R)|clock_BUFGP       |   0.000|
            |    2.438(F)|    0.327(F)|clock_BUFGP       |   0.000|
data<2>     |    3.947(R)|   -1.361(R)|clock_BUFGP       |   0.000|
            |    4.078(F)|    0.837(F)|clock_BUFGP       |   0.000|
data<3>     |    7.670(R)|   -1.384(R)|clock_BUFGP       |   0.000|
            |    2.682(F)|    0.795(F)|clock_BUFGP       |   0.000|
data<4>     |    6.911(R)|   -0.915(R)|clock_BUFGP       |   0.000|
            |    3.682(F)|    0.190(F)|clock_BUFGP       |   0.000|
data<5>     |    4.773(R)|   -0.434(R)|clock_BUFGP       |   0.000|
            |    1.745(F)|    0.623(F)|clock_BUFGP       |   0.000|
data<6>     |    5.420(R)|   -0.528(R)|clock_BUFGP       |   0.000|
            |    2.597(F)|    0.571(F)|clock_BUFGP       |   0.000|
data<7>     |    5.576(R)|   -0.518(R)|clock_BUFGP       |   0.000|
            |    2.963(F)|   -0.319(F)|clock_BUFGP       |   0.000|
ps2_clk     |    3.956(R)|   -1.538(R)|clock_BUFGP       |   0.000|
ps2_data    |    3.986(R)|   -1.572(R)|clock_BUFGP       |   0.000|
------------+------------+------------+------------------+--------+

Clock clock to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
addr<0>     |   11.225(R)|clock_BUFGP       |   0.000|
addr<1>     |   12.141(R)|clock_BUFGP       |   0.000|
addr<2>     |   12.370(R)|clock_BUFGP       |   0.000|
addr<3>     |   12.548(R)|clock_BUFGP       |   0.000|
addr<4>     |   11.735(R)|clock_BUFGP       |   0.000|
addr<5>     |   11.758(R)|clock_BUFGP       |   0.000|
addr<6>     |   11.986(R)|clock_BUFGP       |   0.000|
addr<7>     |   12.163(R)|clock_BUFGP       |   0.000|
addr<8>     |   12.741(R)|clock_BUFGP       |   0.000|
addr<9>     |   12.743(R)|clock_BUFGP       |   0.000|
addr<10>    |    9.850(R)|clock_BUFGP       |   0.000|
addr<11>    |   10.595(R)|clock_BUFGP       |   0.000|
addr<12>    |   12.538(R)|clock_BUFGP       |   0.000|
addr<13>    |   11.649(R)|clock_BUFGP       |   0.000|
addr<14>    |   12.516(R)|clock_BUFGP       |   0.000|
addr<15>    |   10.783(R)|clock_BUFGP       |   0.000|
b<0>        |   11.813(R)|clock_BUFGP       |   0.000|
b<1>        |   12.549(R)|clock_BUFGP       |   0.000|
b<2>        |   13.600(R)|clock_BUFGP       |   0.000|
data<0>     |   21.787(R)|clock_BUFGP       |   0.000|
            |   14.900(F)|clock_BUFGP       |   0.000|
data<1>     |   21.532(R)|clock_BUFGP       |   0.000|
            |   15.787(F)|clock_BUFGP       |   0.000|
data<2>     |   21.332(R)|clock_BUFGP       |   0.000|
            |   14.986(F)|clock_BUFGP       |   0.000|
data<3>     |   20.986(R)|clock_BUFGP       |   0.000|
            |   16.764(F)|clock_BUFGP       |   0.000|
data<4>     |   20.547(R)|clock_BUFGP       |   0.000|
            |   15.427(F)|clock_BUFGP       |   0.000|
data<5>     |   21.199(R)|clock_BUFGP       |   0.000|
            |   14.315(F)|clock_BUFGP       |   0.000|
data<6>     |   21.750(R)|clock_BUFGP       |   0.000|
            |   14.277(F)|clock_BUFGP       |   0.000|
data<7>     |   20.368(R)|clock_BUFGP       |   0.000|
            |   13.783(F)|clock_BUFGP       |   0.000|
diag<0>     |   12.816(R)|clock_BUFGP       |   0.000|
diag<1>     |   12.185(R)|clock_BUFGP       |   0.000|
diag<2>     |    9.729(R)|clock_BUFGP       |   0.000|
diag<5>     |   10.578(R)|clock_BUFGP       |   0.000|
diag<6>     |    9.954(R)|clock_BUFGP       |   0.000|
diag<7>     |    9.950(R)|clock_BUFGP       |   0.000|
g<0>        |   12.181(R)|clock_BUFGP       |   0.000|
g<1>        |   12.883(R)|clock_BUFGP       |   0.000|
g<2>        |   17.151(R)|clock_BUFGP       |   0.000|
hsync_n     |    7.261(R)|clock_BUFGP       |   0.000|
inta        |   16.102(R)|clock_BUFGP       |   0.000|
intr        |   15.831(F)|clock_BUFGP       |   0.000|
r<0>        |   12.181(R)|clock_BUFGP       |   0.000|
r<1>        |   12.883(R)|clock_BUFGP       |   0.000|
r<2>        |   17.487(R)|clock_BUFGP       |   0.000|
readio      |   11.659(R)|clock_BUFGP       |   0.000|
readmem     |   12.181(R)|clock_BUFGP       |   0.000|
vsync_n     |   10.193(R)|clock_BUFGP       |   0.000|
writeio     |   12.660(R)|clock_BUFGP       |   0.000|
writemem    |   10.429(R)|clock_BUFGP       |   0.000|
------------+------------+------------------+--------+

Clock reset_n to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
data<0>     |   16.749(F)|reset_n_BUFGP     |   0.000|
data<1>     |   18.005(F)|reset_n_BUFGP     |   0.000|
data<2>     |   17.064(F)|reset_n_BUFGP     |   0.000|
data<3>     |   18.548(F)|reset_n_BUFGP     |   0.000|
data<4>     |   16.657(F)|reset_n_BUFGP     |   0.000|
data<5>     |   16.867(F)|reset_n_BUFGP     |   0.000|
data<6>     |   16.272(F)|reset_n_BUFGP     |   0.000|
data<7>     |   15.968(F)|reset_n_BUFGP     |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clock
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clock          |   19.258|    7.991|    9.331|    9.205|
reset_n        |   12.349|   12.349|    6.998|    6.998|
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock reset_n
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clock          |         |         |    9.713|         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
ps2_clk        |diag<3>        |   13.322|
ps2_data       |diag<4>        |   12.870|
---------------+---------------+---------+


Analysis completed Wed Nov 15 08:54:56 2006
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 183 MB