Subversion Repositories cpu8080

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Release 8.2.02i Trace 
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

C:\Xilinx\bin\nt\trce.exe -ise C:/Xilinx/ISEexamples/cpu8080/cpu8080.ise
-intstyle ise -e 3 -l 3 -s 4 -xml testbench testbench.ncd -o testbench.twr
testbench.pcf -ucf cpu8080.ucf

Design file:              testbench.ncd
Physical constraint file: testbench.pcf
Device,speed:             xc3s1000,-4 (PRODUCTION 1.39 2006-07-07)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clock
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
data<0>     |    3.965(R)|   -0.833(R)|clock_BUFGP       |   0.000|
            |    3.424(F)|   -0.859(F)|clock_BUFGP       |   0.000|
data<1>     |    3.965(R)|   -0.955(R)|clock_BUFGP       |   0.000|
            |    3.891(F)|   -0.974(F)|clock_BUFGP       |   0.000|
data<2>     |    3.933(R)|   -1.006(R)|clock_BUFGP       |   0.000|
            |    4.165(F)|   -0.929(F)|clock_BUFGP       |   0.000|
data<3>     |    3.825(R)|   -0.872(R)|clock_BUFGP       |   0.000|
            |    3.182(F)|   -0.032(F)|clock_BUFGP       |   0.000|
data<4>     |    4.313(R)|   -1.046(R)|clock_BUFGP       |   0.000|
            |    3.510(F)|   -0.777(F)|clock_BUFGP       |   0.000|
data<5>     |    3.964(R)|   -0.571(R)|clock_BUFGP       |   0.000|
            |    2.671(F)|    0.124(F)|clock_BUFGP       |   0.000|
data<6>     |    3.854(R)|   -0.870(R)|clock_BUFGP       |   0.000|
            |    3.381(F)|   -1.198(F)|clock_BUFGP       |   0.000|
data<7>     |    4.527(R)|    1.071(R)|clock_BUFGP       |   0.000|
            |    2.439(F)|    0.263(F)|clock_BUFGP       |   0.000|
ps2_clk     |    3.956(R)|   -1.538(R)|clock_BUFGP       |   0.000|
ps2_data    |    3.986(R)|   -1.572(R)|clock_BUFGP       |   0.000|
------------+------------+------------+------------------+--------+

Clock clock to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
addr<0>     |   10.858(R)|clock_BUFGP       |   0.000|
addr<1>     |   10.914(R)|clock_BUFGP       |   0.000|
addr<2>     |   11.397(R)|clock_BUFGP       |   0.000|
addr<3>     |   10.704(R)|clock_BUFGP       |   0.000|
addr<4>     |   10.148(R)|clock_BUFGP       |   0.000|
addr<5>     |   10.595(R)|clock_BUFGP       |   0.000|
addr<6>     |   10.832(R)|clock_BUFGP       |   0.000|
addr<7>     |   11.315(R)|clock_BUFGP       |   0.000|
addr<8>     |   11.380(R)|clock_BUFGP       |   0.000|
addr<9>     |   12.357(R)|clock_BUFGP       |   0.000|
addr<10>    |   11.087(R)|clock_BUFGP       |   0.000|
addr<11>    |   11.782(R)|clock_BUFGP       |   0.000|
addr<12>    |   11.691(R)|clock_BUFGP       |   0.000|
addr<13>    |   11.404(R)|clock_BUFGP       |   0.000|
addr<14>    |   11.230(R)|clock_BUFGP       |   0.000|
addr<15>    |   10.677(R)|clock_BUFGP       |   0.000|
b<0>        |   11.124(R)|clock_BUFGP       |   0.000|
b<1>        |   11.857(R)|clock_BUFGP       |   0.000|
b<2>        |   13.235(R)|clock_BUFGP       |   0.000|
data<0>     |   21.320(R)|clock_BUFGP       |   0.000|
            |   13.502(F)|clock_BUFGP       |   0.000|
data<1>     |   21.533(R)|clock_BUFGP       |   0.000|
            |   13.723(F)|clock_BUFGP       |   0.000|
data<2>     |   20.582(R)|clock_BUFGP       |   0.000|
            |   13.229(F)|clock_BUFGP       |   0.000|
data<3>     |   21.046(R)|clock_BUFGP       |   0.000|
            |   13.721(F)|clock_BUFGP       |   0.000|
data<4>     |   20.621(R)|clock_BUFGP       |   0.000|
            |   13.554(F)|clock_BUFGP       |   0.000|
data<5>     |   20.410(R)|clock_BUFGP       |   0.000|
            |   13.301(F)|clock_BUFGP       |   0.000|
data<6>     |   21.348(R)|clock_BUFGP       |   0.000|
            |   13.952(F)|clock_BUFGP       |   0.000|
data<7>     |   19.253(R)|clock_BUFGP       |   0.000|
            |   13.010(F)|clock_BUFGP       |   0.000|
diag<0>     |    9.843(R)|clock_BUFGP       |   0.000|
diag<1>     |    9.474(R)|clock_BUFGP       |   0.000|
diag<2>     |    9.920(R)|clock_BUFGP       |   0.000|
diag<5>     |    9.740(R)|clock_BUFGP       |   0.000|
diag<6>     |    9.927(R)|clock_BUFGP       |   0.000|
diag<7>     |   11.728(R)|clock_BUFGP       |   0.000|
g<0>        |   11.493(R)|clock_BUFGP       |   0.000|
g<1>        |   12.544(R)|clock_BUFGP       |   0.000|
g<2>        |   15.902(R)|clock_BUFGP       |   0.000|
hsync_n     |    7.261(R)|clock_BUFGP       |   0.000|
inta        |   15.482(R)|clock_BUFGP       |   0.000|
intr        |   13.198(F)|clock_BUFGP       |   0.000|
r<0>        |   11.494(R)|clock_BUFGP       |   0.000|
r<1>        |   12.544(R)|clock_BUFGP       |   0.000|
r<2>        |   15.565(R)|clock_BUFGP       |   0.000|
readio      |   10.897(R)|clock_BUFGP       |   0.000|
readmem     |   11.842(R)|clock_BUFGP       |   0.000|
vsync_n     |   10.220(R)|clock_BUFGP       |   0.000|
writeio     |   12.953(R)|clock_BUFGP       |   0.000|
writemem    |   10.310(R)|clock_BUFGP       |   0.000|
------------+------------+------------------+--------+

Clock reset_n to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
data<0>     |   17.482(F)|reset_n_BUFGP     |   0.000|
data<1>     |   18.612(F)|reset_n_BUFGP     |   0.000|
data<2>     |   17.848(F)|reset_n_BUFGP     |   0.000|
data<3>     |   18.500(F)|reset_n_BUFGP     |   0.000|
data<4>     |   16.821(F)|reset_n_BUFGP     |   0.000|
data<5>     |   16.848(F)|reset_n_BUFGP     |   0.000|
data<6>     |   17.372(F)|reset_n_BUFGP     |   0.000|
data<7>     |   16.073(F)|reset_n_BUFGP     |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clock
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clock          |   17.776|    7.712|    9.856|    8.657|
reset_n        |   13.217|   13.217|    9.177|    9.177|
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock reset_n
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clock          |         |         |    9.296|         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
ps2_clk        |diag<3>        |    6.287|
ps2_data       |diag<4>        |    6.287|
---------------+---------------+---------+


Analysis completed Thu Nov 16 20:16:32 2006
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 183 MB