Subversion Repositories cpu8080

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Release 8.2.02i Trace 
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

C:\Xilinx\bin\nt\trce.exe -ise C:/Xilinx/ISEexamples/cpu8080/cpu8080.ise
-intstyle ise -e 3 -l 3 -s 4 -xml testbench testbench.ncd -o testbench.twr
testbench.pcf -ucf cpu8080.ucf

Design file:              testbench.ncd
Physical constraint file: testbench.pcf
Device,speed:             xc3s1000,-4 (PRODUCTION 1.39 2006-07-07)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clock
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
data<0>     |    3.965(R)|   -0.309(R)|clock_BUFGP       |   0.000|
            |    3.199(F)|   -0.202(F)|clock_BUFGP       |   0.000|
data<1>     |    3.965(R)|   -0.033(R)|clock_BUFGP       |   0.000|
            |    3.694(F)|   -0.028(F)|clock_BUFGP       |   0.000|
data<2>     |    3.806(R)|   -0.275(R)|clock_BUFGP       |   0.000|
            |    3.822(F)|   -0.542(F)|clock_BUFGP       |   0.000|
data<3>     |    4.663(R)|   -0.401(R)|clock_BUFGP       |   0.000|
            |    4.530(F)|    0.157(F)|clock_BUFGP       |   0.000|
data<4>     |    3.888(R)|   -0.848(R)|clock_BUFGP       |   0.000|
            |    4.667(F)|   -0.763(F)|clock_BUFGP       |   0.000|
data<5>     |    5.123(R)|   -0.710(R)|clock_BUFGP       |   0.000|
            |    2.118(F)|    0.337(F)|clock_BUFGP       |   0.000|
data<6>     |    4.367(R)|   -0.691(R)|clock_BUFGP       |   0.000|
            |    3.737(F)|    0.118(F)|clock_BUFGP       |   0.000|
data<7>     |    4.557(R)|    0.085(R)|clock_BUFGP       |   0.000|
            |    2.327(F)|    0.669(F)|clock_BUFGP       |   0.000|
ps2_clk     |    3.956(R)|   -1.538(R)|clock_BUFGP       |   0.000|
ps2_data    |    3.986(R)|   -1.572(R)|clock_BUFGP       |   0.000|
------------+------------+------------+------------------+--------+

Clock clock to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
addr<0>     |   11.887(R)|clock_BUFGP       |   0.000|
addr<1>     |   11.680(R)|clock_BUFGP       |   0.000|
addr<2>     |   12.448(R)|clock_BUFGP       |   0.000|
addr<3>     |   12.087(R)|clock_BUFGP       |   0.000|
addr<4>     |   11.631(R)|clock_BUFGP       |   0.000|
addr<5>     |   11.367(R)|clock_BUFGP       |   0.000|
addr<6>     |   11.240(R)|clock_BUFGP       |   0.000|
addr<7>     |   11.104(R)|clock_BUFGP       |   0.000|
addr<8>     |   13.222(R)|clock_BUFGP       |   0.000|
addr<9>     |   13.102(R)|clock_BUFGP       |   0.000|
addr<10>    |   11.433(R)|clock_BUFGP       |   0.000|
addr<11>    |   11.752(R)|clock_BUFGP       |   0.000|
addr<12>    |   11.557(R)|clock_BUFGP       |   0.000|
addr<13>    |   11.823(R)|clock_BUFGP       |   0.000|
addr<14>    |   12.086(R)|clock_BUFGP       |   0.000|
addr<15>    |   10.479(R)|clock_BUFGP       |   0.000|
b<0>        |   11.912(R)|clock_BUFGP       |   0.000|
b<1>        |   13.348(R)|clock_BUFGP       |   0.000|
b<2>        |   13.713(R)|clock_BUFGP       |   0.000|
data<0>     |   21.980(R)|clock_BUFGP       |   0.000|
            |   15.405(F)|clock_BUFGP       |   0.000|
data<1>     |   21.150(R)|clock_BUFGP       |   0.000|
            |   14.607(F)|clock_BUFGP       |   0.000|
data<2>     |   22.440(R)|clock_BUFGP       |   0.000|
            |   14.185(F)|clock_BUFGP       |   0.000|
data<3>     |   21.021(R)|clock_BUFGP       |   0.000|
            |   14.202(F)|clock_BUFGP       |   0.000|
data<4>     |   21.733(R)|clock_BUFGP       |   0.000|
            |   13.899(F)|clock_BUFGP       |   0.000|
data<5>     |   23.040(R)|clock_BUFGP       |   0.000|
            |   14.577(F)|clock_BUFGP       |   0.000|
data<6>     |   21.711(R)|clock_BUFGP       |   0.000|
            |   14.012(F)|clock_BUFGP       |   0.000|
data<7>     |   20.985(R)|clock_BUFGP       |   0.000|
            |   13.492(F)|clock_BUFGP       |   0.000|
diag<0>     |   12.417(R)|clock_BUFGP       |   0.000|
diag<1>     |   13.438(R)|clock_BUFGP       |   0.000|
diag<2>     |   11.244(R)|clock_BUFGP       |   0.000|
diag<5>     |   12.405(R)|clock_BUFGP       |   0.000|
diag<6>     |   10.522(R)|clock_BUFGP       |   0.000|
diag<7>     |   11.767(R)|clock_BUFGP       |   0.000|
g<0>        |   12.302(R)|clock_BUFGP       |   0.000|
g<1>        |   13.004(R)|clock_BUFGP       |   0.000|
g<2>        |   16.784(R)|clock_BUFGP       |   0.000|
hsync_n     |    7.261(R)|clock_BUFGP       |   0.000|
inta        |   15.668(R)|clock_BUFGP       |   0.000|
intr        |   15.964(F)|clock_BUFGP       |   0.000|
r<0>        |   12.282(R)|clock_BUFGP       |   0.000|
r<1>        |   13.004(R)|clock_BUFGP       |   0.000|
r<2>        |   16.890(R)|clock_BUFGP       |   0.000|
readio      |   11.788(R)|clock_BUFGP       |   0.000|
readmem     |   11.248(R)|clock_BUFGP       |   0.000|
vsync_n     |   12.408(R)|clock_BUFGP       |   0.000|
writeio     |   12.165(R)|clock_BUFGP       |   0.000|
writemem    |    9.619(R)|clock_BUFGP       |   0.000|
------------+------------+------------------+--------+

Clock reset_n to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
data<0>     |   18.520(F)|reset_n_BUFGP     |   0.000|
data<1>     |   17.029(F)|reset_n_BUFGP     |   0.000|
data<2>     |   19.000(F)|reset_n_BUFGP     |   0.000|
data<3>     |   18.089(F)|reset_n_BUFGP     |   0.000|
data<4>     |   16.333(F)|reset_n_BUFGP     |   0.000|
data<5>     |   17.180(F)|reset_n_BUFGP     |   0.000|
data<6>     |   15.601(F)|reset_n_BUFGP     |   0.000|
data<7>     |   15.365(F)|reset_n_BUFGP     |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clock
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clock          |   19.080|    8.157|    9.474|    9.681|
reset_n        |   14.538|   14.538|    8.148|    8.148|
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock reset_n
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clock          |         |         |    9.853|         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
ps2_clk        |diag<3>        |    6.287|
ps2_data       |diag<4>        |    6.287|
---------------+---------------+---------+


Analysis completed Sat Nov 18 17:16:24 2006
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 183 MB