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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> <TABLE BORDER CELLSPACING=0 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'> <TD COLSPAN='4'><B>CPU8080 Project Status</B></TD></TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> <TD>cpu8080.ise</TD> <TD BGCOLOR='#FFFF99'><B>Current State:</B></TD> <TD>Programming File Generated</TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> <TD>testbench</TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> <TD ALIGN=LEFT>No Errors</TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> <TD>xc3s1000-4ft256</TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> <TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/*.xmsgs'>182 Warnings (0 filtered)</A></TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD> <TD>ISE 8.2.02i</TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Updated:</B></LI></UL></TD> <TD>Wed Nov 1 08:51:46 2006</TD> </TR> </TABLE> <BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>CPU8080 Partition Summary</B></TD></TR> <TR><TD COLSPAN='4'>No partition information was found.</TD></TR> </TABLE> <BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='5'><B>Device Utilization Summary</B></TD></TR> <TR ALIGN=CENTER BGCOLOR='#FFFF99'> <TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD><B>Note(s)</B></TD> </TR> <TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total Number Slice Registers</B></TD> <TD ALIGN=RIGHT>890</TD> <TD ALIGN=RIGHT>15,360</TD> <TD ALIGN=RIGHT>5%</TD> <TD> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Flip Flops</TD> <TD ALIGN=RIGHT>802</TD> <TD> </TD> <TD> </TD> <TD> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latches</TD> <TD ALIGN=RIGHT>88</TD> <TD> </TD> <TD> </TD> <TD> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD> <TD ALIGN=RIGHT>3,884</TD> <TD ALIGN=RIGHT>15,360</TD> <TD ALIGN=RIGHT>25%</TD> <TD> </TD> </TR> <TR ALIGN=CENTER BGCOLOR='#FFFF99'> <TD ALIGN=LEFT><B>Logic Distribution </B></TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD> <TD ALIGN=RIGHT>3,425</TD> <TD ALIGN=RIGHT>7,680</TD> <TD ALIGN=RIGHT>44%</TD> <TD> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Slices containing only related logic</TD> <TD ALIGN=RIGHT>3,425</TD> <TD ALIGN=RIGHT>3,425</TD> <TD ALIGN=RIGHT>100%</TD> <TD> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Slices containing unrelated logic</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>3,425</TD> <TD ALIGN=RIGHT>0%</TD> <TD> </TD> </TR> <TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total Number 4 input LUTs</B></TD> <TD ALIGN=RIGHT>5,760</TD> <TD ALIGN=RIGHT>15,360</TD> <TD ALIGN=RIGHT>37%</TD> <TD> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number used as logic</TD> <TD ALIGN=RIGHT>3,884</TD> <TD> </TD> <TD> </TD> <TD> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number used as a route-thru</TD> <TD ALIGN=RIGHT>196</TD> <TD> </TD> <TD> </TD> <TD> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number used for Dual Port RAMs</TD> <TD ALIGN=RIGHT>1,680</TD> <TD> </TD> <TD> </TD> <TD> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='testbench_map.mrp?&DataKey=IOBProperties'>IOBs</A></TD> <TD ALIGN=RIGHT>44</TD> <TD ALIGN=RIGHT>173</TD> <TD ALIGN=RIGHT>25%</TD> <TD> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> IOB Flip Flops</TD> <TD ALIGN=RIGHT>9</TD> <TD> </TD> <TD> </TD> <TD> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Block RAMs</TD> <TD ALIGN=RIGHT>2</TD> <TD ALIGN=RIGHT>24</TD> <TD ALIGN=RIGHT>8%</TD> <TD> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MULT18X18s</TD> <TD ALIGN=RIGHT>1</TD> <TD ALIGN=RIGHT>24</TD> <TD ALIGN=RIGHT>4%</TD> <TD> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of GCLKs</TD> <TD ALIGN=RIGHT>3</TD> <TD ALIGN=RIGHT>8</TD> <TD ALIGN=RIGHT>37%</TD> <TD> </TD> </TR> <TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total equivalent gate count for design</B></TD> <TD ALIGN=RIGHT>278,010</TD> <TD> </TD> <TD> </TD> <TD> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Additional JTAG gate count for IOBs</TD> <TD ALIGN=RIGHT>2,112</TD> <TD> </TD> <TD> </TD> <TD> </TD> </TR> </TABLE> <BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>Performance Summary</B></TD></TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD> <TD>0</TD> <TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD> <TD><A HREF_DISABLED='testbench.pad?&DataKey=PinoutData'>Pinout Report</A></TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD> <TD><A HREF_DISABLED='testbench.unroutes'>All Signals Completely Routed</A></TD> <TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD> <TD><A HREF_DISABLED='testbench.par?&DataKey=ClocksData'>Clock Report</A></TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD> <TD><A HREF_DISABLED='testbench.par?&DataKey=ConstraintsData'>All Constraints Met</A></TD> <TD BGCOLOR='#FFFF99'><B> </B></TD> <TD> </TD> </TR> </TABLE> <BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='6'><B>Detailed Reports</B></TD></TR> <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT><B>Infos</B></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='testbench.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Nov 1 08:45:16 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>167 Warnings (0 filtered)</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>10 Infos (0 filtered)</A></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='testbench.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed Nov 1 08:45:26 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='testbench_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed Nov 1 08:45:44 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>9 Warnings (0 filtered)</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>3 Infos (0 filtered)</A></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='testbench.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed Nov 1 08:51:14 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/par.xmsgs'>2 Warnings (0 filtered)</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/par.xmsgs'>2 Infos (0 filtered)</A></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='testbench.twr'>Static Timing Report</A></TD><TD>Current</TD><TD>Wed Nov 1 08:51:26 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/trce.xmsgs'>2 Infos (0 filtered)</A></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='testbench.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Wed Nov 1 08:51:48 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/bitgen.xmsgs'>4 Warnings (0 filtered)</A></TD><TD ALIGN=LEFT>0</TD></TR> </TABLE> <BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='3'><B>Secondary Reports</B></TD></TR> <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD></TR> <TR ALIGN=LEFT><TD>Xplorer Report</TD><TD> </TD><TD> </TD></TR> </TABLE> </BODY></HTML>
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