URL
https://opencores.org/ocsvn/cpu8080/cpu8080/trunk
Subversion Repositories cpu8080
[/] [cpu8080/] [trunk/] [project/] [tmpRTVStore.xwv] - Rev 33
Compare with Previous | Blame | View Log
inta inta_DIFF waitr hsync_n hsync_n_DIFF vsync_n vsync_n_DIFF reset clock addr addr /testbench/addr addr_DIFF addr_DIFF /testbench/addr_DIFF data data /testbench/data r r /testbench/r r_DIFF r_DIFF /testbench/r_DIFF g g /testbench/g g_DIFF g_DIFF /testbench/g_DIFF ! b " b /testbench/b! ! # b_DIFF $ b_DIFF /testbench/b_DIFF# # readmem /testbench/readmem readmem_DIFF /testbench/readmem_DIFF writemem /testbench/writemem writemem_DIFF /testbench/writemem_DIFF readio /testbench/readio readio_DIFF /testbench/readio_DIFF writeio /testbench/writeio writeio_DIFF /testbench/writeio_DIFF intr /testbench/intr intr_DIFF /testbench/intr_DIFFinta /testbench/intainta_DIFF /testbench/inta_DIFF waitr /testbench/waitr hsync_n /testbench/hsync_n hsync_n_DIFF /testbench/hsync_n_DIFF vsync_n /testbench/vsync_n vsync_n_DIFF /testbench/vsync_n_DIFF reset /testbench/reset clock /testbench/clock addr /testbench/addr ! " # addr_DIFF /testbench/addr_DIFF$ % & ' ( ) * + , - . / 0 1 2 3 4 data /testbench/data5 6 7 8 9 : ; < = r /testbench/r> ? @ A r_DIFF /testbench/r_DIFFB C D E g /testbench/gF G H I g_DIFF /testbench/g_DIFFJ K L M "1Hb)XN7uo/P5}B6פ81;^8<?.Bl_C$HMUIN.KO[|PAU<rVh\tsUyܗ|꾃kگLе-ƻ*%2D 2E zE zHH