OpenCores
URL https://opencores.org/ocsvn/cpu8080/cpu8080/trunk

Subversion Repositories cpu8080

[/] [cpu8080/] [trunk/] [project/] [xst/] [dump.xst/] [testbench.prj/] [ntrc.scr] - Rev 33

Compare with Previous | Blame | View Log

set -xsthdpdir ./xst\
set -checkcmdline no
run -ifn testbench.prj -ifmt mixed -ofn testbench -ofmt NGC -p xc3s1000-4-ft256 -top testbench -opt_mode Speed -opt_level 1 -iuc NO -lso testbench.lso -keep_hierarchy NO -rtlview Yes -glob_opt AllClockNets -read_cores YES -write_timing_constraints NO -cross_clock_analysis NO -hierarchy_separator / -bus_delimiter <> -case maintain -slice_utilization_ratio 100 -verilog2001 YES -fsm_extract YES -fsm_encoding Auto -safe_implementation No -fsm_style lut -ram_extract Yes -ram_style Auto -rom_extract Yes -mux_style Auto -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -rom_style Auto -mux_extract YES -resource_sharing YES -mult_style auto -iobuf YES -max_fanout 500 -bufg 8 -register_duplication YES -register_balancing No -slice_packing YES -optimize_primitives NO -use_clock_enable Yes -use_sync_set Yes -use_sync_reset Yes -iob auto -equivalent_register_removal YES -slice_utilization_ratio_maxmargin 5 -crit Speed -power 1 -mapstyle lut -fsm_encoding Auto -t XILINX -addsub_extract yes
 

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.