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[/] [csa/] [trunk/] [quartus10/] [csa_fpga.v] - Rev 34
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// this file is the test circuit // author: Simom Panti // module csa_fpga( output bell , input clk , input rst , input flaga , input flagb , input flagc , output slcs , output pktend , output reg sloe , output reg slwr , output reg slrd , output reg [ 1:0] fifoadr , inout [15:0] fd , input ifclk , output [ 7:0] led , output [ 3:0] ledseg , output [ 7:0] seg_d ); wire usbclk = ifclk; wire ep6_havedata = flaga; wire ep2_haveroom = flagc; wire ep8_havedata = flagb; assign bell = 1'h1; `define CNT_WIDTH 25 `define STA_WIDTH 4 //////////////////////////////////////////////////////////////////////////////// // led segement control //////////////////////////////////////////////////////////////////////////////// ledseg_cnt ledseg_cnt( .clk (usbclk) , .rst (rst) , .data (usb_dat_in) , .seg (ledseg) , .segd (seg_d) ); //////////////////////////////////////////////////////////////////////////////// // usb interface //////////////////////////////////////////////////////////////////////////////// assign slcs =1'h0; assign pktend=1'h1; `define EP2_W 2'h0 `define EP6_R 2'h1 `define EP8_R 2'h2 `define NO_ACT 2'h3 reg [ 1:0] last_action; reg [15:0] usb_dat_out; reg [15:0] usb_dat_in; always @(posedge usbclk) if(ep6_havedata) begin sloe<=1'h0; fifoadr<=2'h2; slrd<=1'h0; slwr<=1'h1; last_action<=`EP6_R; end else if(ep8_havedata) begin sloe<=1'h0; fifoadr<=2'h3; slrd<=1'h0; slwr<=1'h1; last_action<=`EP8_R; end else if(ep2_haveroom) begin // ouput data sloe<=1'h1; fifoadr<=2'h0; slwr<=1'h0; slrd<=1'h1; last_action<=`EP2_W; end else begin sloe<=1'h1; fifoadr<=2'h0; slwr<=1'h1; slrd<=1'h1; last_action<=`NO_ACT; end always @(posedge usbclk) if(last_action==`EP8_R ) usb_dat_in<=fd; assign fd=(sloe)?usb_dat_out:16'hzzzz; //////////////////////////////////////////////////////////////////////////////// // csa decrypt module //////////////////////////////////////////////////////////////////////////////// decrypt csa_decrypt( . clk (usbclk) ,. rst (rst) ,. ck (64'h0000000000000000) ,. key_en (1'h0) ,. even_odd (1'h0) ,. en () ,. encrypted () ,. decrypted () ,. invalid () ); endmodule
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