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[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] [verilog/] [dbg_cpu_defines.v] - Rev 100
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////////////////////////////////////////////////////////////////////// //// //// //// dbg_cpu_defines.v //// //// //// //// //// //// This file is part of the SoC/OpenRISC Development Interface //// //// http://www.opencores.org/projects/DebugInterface/ //// //// //// //// Author(s): //// //// Igor Mohor (igorm@opencores.org) //// //// //// //// //// //// All additional information is avaliable in the README.txt //// //// file. //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 - 2004 Authors //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // // // Defining commands for cpu module //`define CPU_STATUS 3'h0 `define CPU_WRITE8 3'h1 `define CPU_WRITE32 3'h2 `define CPU_WRITE_REG 3'h3 `define CPU_GO 3'h4 `define CPU_READ8 3'h5 `define CPU_READ32 3'h6 `define CPU_READ_REG 3'h7 // Number of supported cpus `define CPU_NUM 2 // Registers addresses `define CPUOP_ADR 2'd0 `define CPUSEL_ADR 2'd1
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