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[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] [verilog/] [jtag_chain.v] - Rev 36
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////////////////////////////////////////////////////////////////////// //// //// //// jtag_chain.v //// //// //// //// //// //// This file is part of the SoC/OpenRISC Development Interface //// //// http://www.opencores.org/projects/DebugInterface/ //// //// //// //// //// //// Author(s): //// //// Igor Mohor //// //// igorm@opencores.org //// //// //// //// //// //// All additional information is avaliable in the README.txt //// //// file. //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000, 2001, 2002 Authors //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // // // // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "dbg_defines.v" // Top module module jtag_chain ( capture_dr_i, shift_dr_i, update_dr_i, extest_selected_i, bs_chain_i, bs_chain_o ); parameter Tp = 1; input capture_dr_i; input shift_dr_i; input update_dr_i; input extest_selected_i; input bs_chain_i; output bs_chain_o; assign bs_chain_o = 0; endmodule
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