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[/] [ddr2_sdram/] [trunk/] [Top_Modul_VHDL_bitgen.xwbt] - Rev 4

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INTSTYLE=ise
INFILE=F:\Data_Temp_Ordner\Xilinx\Projekte\Test_Prj_VHDL\Prj_12_DDR2\Prj_12_DDR2\Top_Modul_VHDL.ncd
OUTFILE=F:\Data_Temp_Ordner\Xilinx\Projekte\Test_Prj_VHDL\Prj_12_DDR2\Prj_12_DDR2\Top_Modul_VHDL.bit
FAMILY=Spartan3A and Spartan3AN
PART=xc3s700a-4fg484
WORKINGDIR=F:\Data_Temp_Ordner\Xilinx\Projekte\Test_Prj_VHDL\Prj_12_DDR2\Prj_12_DDR2
LICENSE=WebPack
USER_INFO=205456775_0_0_536

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